Hi,
I would like to know what is the recommended connection scheme for connecting two TMS320C6424 DSPs in parallel to x16 Microchip SLIC using the McASP0 interface (TDM)?
Here is an example of what I would like to achieve:
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Hi,
I would like to know what is the recommended connection scheme for connecting two TMS320C6424 DSPs in parallel to x16 Microchip SLIC using the McASP0 interface (TDM)?
Here is an example of what I would like to achieve:
Hello Haim Anaya,
Thank you for the Query.
The link below lists the datasheet and the user guides for the DSP.
https://www.ti.com/product/TMS320C6424
The Key requirement is the SLIC interface and this is a third part solution.
It would be best for you to internally work on a scheme based on the device/end application expertise or reach out to the SLIC solution provider who might have experience providing solutions for similar experience.
For the ethernet interface please refer below link
https://www.ti.com/interface/ethernet/phys/overview.html
You can also look at the applications path on TI.com to find solution that matches the application you are considering.
Regards,
Sreenivasa
The question is not about the slave device (in this case the SLIC) connected to the interface, the question was about the DSPs. I was asking whether this way of connecting both DSP's TDM-TX output port to the same PCM_DX line will cause a contention or not? and if this is the correct way to connect two DSPs to the same PCM bus (on which will be eventually 32 SLIC)?
Hello Haim Anaya,
Thank you for clarifying.
The configuration shown in the diagram is expected to result in signal contention and would not be recommended. There may be ways to implement bus switching but this could have effect on the clock/signal quality.
We do not have any example interface implementation similar to what you are looking for that could be referenced. These are application specific.
it is recommended to perform simulations/prototyping these concepts.
Regards,
Sreenivasa
Hello,
I would like to know please whether the DX/DR pins (PIN K3(DR0/GPIO100), PIN H3 (DR1/GPIO110), K2(DX0/GPIO104),G2 (DX1/GPIO107) ),are open drain? and what is the input resistance of them?
Thanks,
Haim.
Hello Haim Anaya,
Thank you for checking. For the queries Please refer to the datasheet and the General-Purpose Input/Output (GPIO) User's Guide for the required details.
https://www.ti.com/lit/ds/symlink/tms320c6424.pdf
https://www.ti.com/lit/ug/spruem8a/spruem8a.pdf
Regards,
Sreenivasa