Is there a way to view the contents of L1 and L2 cache on the ARM Cortex-A15? I don't see any ability to do this in code composer studio for this particular processor.
Is there any way to guarantee or overwrite the contents of the caches? My understanding is that invalidating the caches only clears the valid bit for a cache line, but doesn't actually clear the contents in the cache line. Another source indicated that the caches are in an undefined state coming out of reset and need to invalidated prior to use, so reset doesn't offer any guarantees. The preload instructions (PLD, PLDW, PLI) are only hint instructions, which doesn't guarantee they'll execute to modify the caches.