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AM5749: view and overwrite ARM Cortex-A15 cache contents

Part Number: AM5749

Is there a way to view the contents of L1 and L2 cache on the ARM Cortex-A15?  I don't see any ability to do this in code composer studio for this particular processor.

Is there any way to guarantee or overwrite the contents of the caches?  My understanding is that invalidating the caches only clears the valid bit for a cache line, but doesn't actually clear the contents in the cache line.  Another source indicated that the caches are in an undefined state coming out of reset and need to invalidated prior to use, so reset doesn't offer any guarantees.  The preload instructions (PLD, PLDW, PLI) are only hint instructions, which doesn't guarantee they'll execute to modify the caches.

  • Hello,
    On the AM57xx's Cortex-A15 the dumping of the caches is blocked in non-secure mode but is possible in secure mode via coprocessor sequences.  Secure mode in the Cortex-A15 context is part of the Trustzone feature set.
    TI provides two types of devices "GP-general purpose" and "HS-high-security".  On a GP device the trustzone-secure mode is completely blocked so direct inspect of the cache memories is impossible.  On HS devices, cache inspect is possible if a secure environment is properly created and called.  Service calls which are handed in secure mode must pass through strong public/private key authentication interfaces.  Additionally CP15 lockouts must not be activated.
    If you are looking for ways to scrub the data ram contents for the L1/L2 caches it might be the 100% way is a long power cycle.   Practically speaking, if you invalidate the caches, then load in a large amount of dummy data the sensitive values would have been overwritten.

    Richard W.