Hello experts,
we have done a benchmark of PCIe communications between two TDA4VM evaluation boards
we are in gen3, 2x lane width, we use the ARM cores to do the PCIe bring up and then the C7x cores to do the benchmark
the test is composed of a simple 'for' loop where we write data to the endpoint
we get this result, however we have trouble interpreting it.
--> do you have any idea why the peak is at 128 bytes?
--> more generally, is the graph shape as expected by TI experts ?
Best,
Clement