AM5718-HIREL: Clock output jitter of QSPI

Yuya

Part Number: AM5718-HIREL

Hi Support Team,

I'd like to use QSPI of AM5718-hirel as master mode.
In this case, what is the Period jitter of QSPI clock output(qspi1_sclk)?
I could not find the description in the datasheet.

Best Regards,

over 2 years ago

0 Yuya over 2 years ago

Prodigy 200 points

Hi,

Could anyone please help us here? Thanks.

0 kcastille over 2 years ago in reply to Yuya

TI__Guru 51042 points

Yuya,

We don't spec the jitter for that clock interface.

Can you give the background for your question? We may be able to provide an alternate spec depending on your question.

Regards,

Kyle

0 Yuya over 2 years ago in reply to kcastille

Prodigy 200 points

Hi Kyle,

Thank you for your reply.

I am considering the SCLK frequency for read access to QSPI flash memory on the custom board using the AM5718-hirel.
As shown in the figure below, the setup time (③ in the figure) during read access is determined by the difference between the SCLK period (① in the figure) and the output delay time (② in the figure).
Therefore, I am looking for information on the worst time of the SCLK period to ensure that the setup time meets the datasheet requirements.

QSPI Read

Best Regards,

0 Yuya over 2 years ago in reply to Yuya

Prodigy 200 points

Hi Kyle,

Could you please update me on this issue?
I am looking forward to the response from you.

Best Regards,
Yuya

+1 B.C. over 2 years ago in reply to Yuya

TI__Genius 16705 points

The clock jitter is dominated by PLL jitter, which can be up to 2.5%.

0 Yuya over 2 years ago in reply to B.C.

Prodigy 200 points

Thank you for your reply.
You've been very helpful.

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AM5718-HIREL: Clock output jitter of QSPI