TMS320C6657: The memory configuration in the second boot.

Frand Green

Part Number: TMS320C6657

Hi,

I complete two boots process in my system, first boot the ddr init program,second boot my real app program. And in the ddr init program all cmd sections are defined in L2 memory, they work well ,there is no problem.

Then in my real app program, the sections are define in L2 or DDR, and i found that where several sections defined seriously affect the program work result. They are .const/.cinit/.switch sections, when i define any one

of them in the DDR,my app program can not work normally.when i put all the three sections in L2, app program canwork well.

My question is why this happens?

My final cmd is as below

-heap 0x4000000 /* 64MB */
-stack 0x4000 /* 16KB */

MEMORY
{
LOCAL_L2_SRAM: o = 0x00800000 l = 0x00100000 /* 1MB LOCAL L2 SRAM */
LOCAL_L1P_SRAM: o = 0x00E00000 l = 0x00008000 /* 32kB LOCAL L1P SRAM */
LOCAL_L1D_SRAM: o = 0x00F00000 l = 0x00008000 /* 32kB LOCAL L1D SRAM */

MSMSRAM: o = 0x0C000000 l = 0x00100000 /* 1MB Multicore shared Memmory */
CORE0_L2_SRAM_STACK: o = 0x10800000 l = 0x00004000 /* 1024kB CORE0 L2/SRAM */
CORE0_L2_SRAM: o = 0x10804000 l = 0x000FBFFC /* 1024kB CORE0 L2/SRAM ,last four bytes reserved for magic address*/

CORE0_L1P_SRAM: o = 0x10E00000 l = 0x00008000 /* 32kB CORE0 L1P/SRAM */
CORE0_L1D_SRAM: o = 0x10F00000 l = 0x00008000 /* 32kB L1D/SRAM */

EMIF16_CE0: o = 0x70000000 l = 0x04000000 /* 64MB EMIF16 CE0 Data Memory */
EMIF16_CE1: o = 0x74000000 l = 0x04000000 /* 64MB EMIF16 CE1 Data Memory */
EMIF16_CE2: o = 0x78000000 l = 0x04000000 /* 64MB EMIF16 CE2 Data Memory */
EMIF16_CE3: o = 0x7C000000 l = 0x04000000 /* 64MB EMIF16 CE3 Data Memory */

/*DDR3: o = 0x80000000 l = 0x40000000*/ /* 1GB DDR3 */
DDR3_GENERAL: o = 0x80000000 l = 0x3BEF6800 /* 1GB - 2KB*19 - 1MB DDR3 */
DDR3_COMM: o = 0xBBEF6800 l = 0x9800 /* 2KB*19 = 38KB */
DDR3_SCF: o = 0xBBF00000 l = 0xFF000 /* 大小1M-4K */
DDR3_HANDSHAKE: o = 0xBBFFF000 l = 0x0400 /* 大小1K */
DDR3_ERR_INFO: o = 0xBBFFF400 l = 0x0C00 /* 大小3K */
DDR3_HEAP: o = 0xBC000000 l = 0x4000000 /* 大小64MB */
}

SECTIONS
{
.text > CORE0_L2_SRAM
.stack > CORE0_L2_SRAM_STACK
.bss > CORE0_L2_SRAM
.cio > CORE0_L2_SRAM
.const > CORE0_L2_SRAM
.data > CORE0_L2_SRAM
.switch > CORE0_L2_SRAM
.sysmem > DDR3_HEAP
.far > CORE0_L2_SRAM
.args > CORE0_L2_SRAM
.ppinfo > CORE0_L2_SRAM
.ppdata > CORE0_L2_SRAM

.l2_int > DDR3_GENERAL
.vects > DDR3_GENERAL

/* COFF sections */
.pinit > DDR3_GENERAL
.cinit > CORE0_L2_SRAM

/* EABI sections */
.binit > DDR3_GENERAL
.init_array > DDR3_GENERAL
.neardata > CORE0_L2_SRAM
.fardata > CORE0_L2_SRAM
.rodata > CORE0_L2_SRAM
.c6xabi.exidx > CORE0_L2_SRAM
.c6xabi.extab > CORE0_L2_SRAM
.csl_vect > CORE0_L2_SRAM /* csl vect code */

.rtdata > CORE0_L2_SRAM
.rtcode > CORE0_L2_SRAM
.nrtdata > DDR3_GENERAL
.nrtcode > DDR3_GENERAL
}

over 2 years ago

0 Victor Kazmirenko over 2 years ago

Guru 13202 points

Hello!

I did not check your configurations, can't say they are okay or not. Nevertheless, do you perform that on EVM or on your custom board? If that is custom board, did you try any memory test before?

0 Frand Green over 2 years ago in reply to Victor Kazmirenko

Prodigy 110 points

Hello!

I perform that on my board.I have test my whole ddr memory, by writing and checking, and i put some test code in the ddr, they work well. So i confirm that the memory is ok.

0 Shankari G over 2 years ago in reply to Frand Green

TI__Mastermind 25095 points

Frand,

If you have C6657 EVM, try to do the same test and check the behaviour.

If the test works in Ti-EVM and not in the custom board, then it is easy to sort out the difference and the issue.

And also try to perform the platform test on your custom EVM which encloses the internal and external memory test.

The linker.cmd of the platform test of Processor SDK will act as a good reference point for the memory sections.

I have attached the linker.cmd of the platform test here.

/******************************************************************************
 * Copyright (c) 2010-2011 Texas Instruments Incorporated - http://www.ti.com
 * 
 *  Redistribution and use in source and binary forms, with or without 
 *  modification, are permitted provided that the following conditions 
 *  are met:
 *
 *    Redistributions of source code must retain the above copyright 
 *    notice, this list of conditions and the following disclaimer.
 *
 *    Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in the 
 *    documentation and/or other materials provided with the   
 *    distribution.
 *
 *    Neither the name of Texas Instruments Incorporated nor the names of
 *    its contributors may be used to endorse or promote products derived
 *    from this software without specific prior written permission.
 *
 *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 
 *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 
 *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
 *  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 
 *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 
 *  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 
 *  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
 *  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
 *  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 
 *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 
 *  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 * 
 *****************************************************************************/
/*
 *  Linker command file
 *
 */

-c
-heap  0x41000
-stack 0xa000

/* Memory Map 1 - the default */
MEMORY
{
    L1PSRAM (RWX)  : org = 0x0E00000, len = 0x7FFF
    L1DSRAM (RWX)  : org = 0x0F00000, len = 0x7FFF 

    L2SRAM (RWX)   : org = 0x0800000, len = 0x080000
    MSMCSRAM (RWX) : org = 0xc000000, len = 0x100000
    DDR3 (RWX)     : org = 0x80000000,len = 0x20000000
}

SECTIONS
{
    .csl_vect   >       MSMCSRAM
    .text       >       MSMCSRAM
    GROUP (NEAR_DP)
    {
    .neardata
    .rodata 
    .bss
    } load > MSMCSRAM
    .stack      >       MSMCSRAM
    .cinit      >       MSMCSRAM
    .cio        >       MSMCSRAM
    .const      >       MSMCSRAM
    .data       >       MSMCSRAM
    .switch     >       MSMCSRAM
    .sysmem     >       MSMCSRAM
    .far        >       MSMCSRAM
    .testMem    >       MSMCSRAM
    .fardata    >       MSMCSRAM
    platform_lib > 		MSMCSRAM
}

First, let us take the working "*.cmd: file and keep doing changes in the memory sections, "one by one ", so that it is easy to eradicate the errors...

Regards

Shankari G

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TMS320C6657: The memory configuration in the second boot.