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TDA4VM: DDR ATYPE 3 and A72 cache coherent

Part Number: TDA4VM


1. We modify DDR ATYPE value, default is 0, we set ATYPE 3 with R5F and C66.

2. As the describe, when set ATYPE=3, A72 need manually make coherent when A72 comubication with C66.

3. So, in A72 code, we called appMemCacheWb (also call dsb, memory barrier) and then data send. When C66 received, called appMemCacheWbInv.

    But, we find data not correct, some data is error. When we set ATYPE=0, the data not error.

4. Then, viewing the appMemCacheWb,  and add print info in the driver dma-buf of linux kernel code.


  But we find the cache related function not called, and the calllbak function is NULL


Now, we I don't how deal this question and give us some advice pelease, thanks.