TDA4VM-Q1: SGMII EYE Validation on custom TDA4VM board.

Hi Shreyas,

After we disabled Pre-post cursors , we checked the eye pattern but seems there is no effect and no improvement in eye diagram.

By default DRVCTRL_C0M_OVRD_PREG__DRVCTRL_CP1_OVRD_PREG register value is 0x0107F017F, we changed it to 0x108 and also 0x017F007F.

Can you please help us further on this.

Regards,

Chaitanya

Any update on the same?

Regards,

Chaitanya

Are you using the 2-Lane or 4-Lane SERDES? Are you using the 100M or 156.25M ref clk?

Below is the update for 2-L serdes I found for 100MHz.

/cfs-file/__key/communityserver-discussions-components-files/791/csl_5F00_wiz16m_5F00_cs_5F00_refclk100MHz_5F00_20b_5F00_SGMII.c

Also, based on the validation findings, there were these registers updated to pass the compliance.

DRVCTRL_AMPBOOST_TUNE_PREG = 0x7

DRVCTRL_EDGEBOOST_TUNE_PREG =0x2

CMN_RESCAL_TXOFFSET_PREG=0x27

Please let me know.

Hi Shreyas,

We have applied the above patch in our code and also  we configured  this register DRVCTRL_C0M_OVRD_PREG__DRVCTRL_CP1_OVRD_PREG value 0x108, Now we could see the improvement in our EYE diagram. Please find the captured waveform on SGMII TX side.

NOTE: In the patch we commented the line setting MODE23_PREG because it didn't work untill I removed this line.

//CSL_FINSR(*(volatile uint32_t *)(&sierra_sds_reg->LN_CTRL_CDBREG[laneNum].PLLCTRL_FBDIV_MODE01_PREG__PLLCTRL_FBDIV_MODE23_PREG),31,16,(uint32_t)0x0106);

Can you please let me know, Is the waveform is fine or not?

Regards,

Sesha Venkata Harikrishna.

Hi Shreyas,

Any update on the above. can you provide us your feedback.

Regards,

Chaitanya

Chaitanya,

The amplitude seems to have significantly improved from before. The required electrical specs as per IEEE 802.3ap clause 70-7 of 800mV differential amplitude are also met.

I assume that you are not seeing concerns with the receiver side when sending out the transmitter signals from SoC.