TMS320C6727B: WE toggle twice in 1 write cycle

This is an older device and may take some time to try and get an answer.

--Paul

Shine, can you dump all of the EMIF register configuration, as show in EMIF user's guide.  There may be something wrong with your configuration

Regards,

James

Hello James,

Thanks for your help.

Below is the configuration of EMIF registers.

SDTIMR = 0x31114610;
SDSRETR = 0x1F;
SDRCR = 0x9C4;
SDCR = 0x4721;
Delay(1100);
SDRCR = 0x61A;

A1CR = 0x3FFFFFFD;

Thanks.
Rgds
Shine

Shine, it appears to be working in 8bit mode.  Can you read out the register value for A1CR (not just what is configured in code)?  It may not be getting written correctly.

Also, how is variable Flash_5555h declared?  Is it defined as a byte (8bit) or word (16bit) element?

Regards,

James

Hi James,

Thanks for your help.

1. Yes, customer printf the A1CR register, it shows the value is 0x3FFFFFFD

2.Flash_5555h is defined as below：

#define Flash_5555h         *(unsigned int *)0x9000AAAA

Thanks.
Rgds
Shine

Shine, can you show the processor side of the schematic connection?  Are you showing signal EM_WE or EM_WE_DQM in the scope shot?

Regards,

James

Hi James,

Thanks for your help.

(1) Below is the processor side of the schematic connection.

Flash_CE pin is connected to CS2 through FPGA VHDL code. 
CS_2 <= FLASH_CE;

Because DSP is BGA package, he used VHDL code to connect the EMIF pin to FPGA and observe the timing wave on FPGA side.

(2) It shows EM_WE in the scope shot.

Thanks.
Rgds
Shine

Shine, i'm not sure what is going on here.  Does the write complete successfully?  Does the same behavior happen on a read?

REgards,

James

Hi James,

Thanks for your help.

1.  The read operation failed, too. 

2. Because he failed to write data to fixed address, so he can't read data correctly. But the read timing wave is the same to the write timing wave. 

Thanks.
Rgds
Shine

Hi James,

Customer resolved the issue according to your advice.

Thanks.
Rgds
Shine