Read/Write EMIF 64 bits from C/C++

Hi Christophe,

Virtex 5 FPGA contains MicroBlaze and PowerPC soft core but they both are 32 bit, so you cant directly use an embedded processor. If you want to use embedded processor then you have to read 32 bits at a time only(half the maximum performance). Same goes for DSP processor too, I think.

Or you can define a 64 bit data bus directly in your FPGA, but I am not sure about the amount of hardware logic and BRAM it would consume.

Anyways, as you said, more details would help .

1. What is more important for you? Speed or Resolution?

2. What is the system clock you are using for the FPGA? This can help us determine the Processor Bus Frequency for MicroBlaze inside FPGA and in turn help to know, how much compromise needs to be done in terms of access performance.

Regards,

Sid

Hi Sid,

Thank you for your kind answer.

We already have the logic for a 64 bits bus in the FPGA. (and we don't have any softcore in the FPGA).

I know it's possible to write 64 bits at a time using the EDMA engine to transfer data from / to the FPGA. (see here : https://community.ti.com/forums/t/7052.aspx)

I would like to do that but only by doing memory-type access from the DSP. My problem being that I don't know how to write C code that will tell the compiler to do that. (maybe it's not possible in C ?)

Regards,

Christophe

Hi Christophe,

Are you using CCS for transferring data? Then for a CCS project, there exists a linker file (.cmd) wherein you map memory sections. Once you define a particular section in a particular memory bank of DSP, you can easily define an array of 64 bits to belong to that section using #pragma.

Once you get access to such a section, transferring data should be easy. :)

Hope this helps.

Regards,

Sid

Hi Sid,

I don't know what you mean with : "are you using CCS for transferring data ?".

What I have is a C program compiled with CCS v4.0.x running on the DSP and what I would like to do is access a 64 bits register on the FPGA connected on the EMIFA (64 bits).

We used to have a 32 bits EMIF bus and I could access the 32 bits register using that C code :

static inline void fpga_write(uint32 addr, uint32 value)
{
  volatile uint32 * p = (uint32 *)addr;
  *p = value;
}

static inline uint32 fpga_read(uint32 addr)
{
  return *(volatile uint32 *)addr;
}

But now I would like to write and read 64 bits at a time (if it's even possible).

With the following code :

static inline void fpga_write64(uint32 addr, uint64 value)
{
 /* insert whatever is missing*/
}

static inline uint64 fpga_read64(uint32 addr)
{
/* insert whatever is missing*/
}

By dissembling the first code I saw it was using the STW op-code and what I probably want is that the C compiled code generates an STDW (store double word) for this.

Hi Christophe,

Umm well, I am not sure, but GNU-GCC standards support "long long int" as 64-bit variable. If this DSP processor supports 64-bit EMIF (am not sure about this), then this datatype should use corresponding opcode STDW for this.

Otherwise, you may have to resort back to 32-bit operation at a time.

Regards,

Sid

Thanks for trying to help me :)

• The DSP supports EMIF 64 bits (EMIFA is configured for ASYNC_64)
• The DSP compiler supports 64 bit data type (long long)

Hi Christophe,

I am glad you found it. :)

Regards,

Sid

Thanks for your very friendly help !

Hi Christopher,

I am using the DSK 6416 and I need to connect it to the Virtex-5 through the DSK's EMIF.

May I know the interface you used to connect both of these ?  Did you use the DDR-2 RAM on the FPGA board ?

Awaiting a quick reply from your end.

Thanks,

Varun