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TDA4VM-Q1: TDA4VL 3- terminal capacitors quantity optimization

Part Number: TDA4VM-Q1
Other Parts Discussed in Thread: TDA4VL

Hi team,

   we find that the TDA4VL PDN performance is very good although we delete some 3-terminal capacitors. we come to this conclusion based on the PDN requirement document "TDA4AL_VL_VME_Prlm_PI_Rcmds_v0.3.pdf".

the simulation result indicates that we can delete these 3-terminal capacitors which locate beside the CPU: four 1uF for VDD_CPU_AVS; 7 10uF and 5 1uF for VDD_CORE_0V8; one 10uF and three 1uF for VDD_MCU_0V85_REG; 2 10uF and 7 1uF for VDD_DDR_1V1_REG. please help to if there is more PDN requirement for TDA4VL besides the document  "TDA4AL_VL_VME_Prlm_PI_Rcmds_v0.3.pdf" and if there is any risk if we delete these 3-terminal capacitors. tks.

  • We have no additional PDN requirements beyond this document.  The recommended decoupling provided is based on our EVM implementation.  Your PCB will perform differently than our EVM, and thus needs to be modeled/simulated to determine its performance.  During the simulation, variations of capacitors can be tried to determine how the performance is affected/optimized.  Also remember simulations are just an estimate, and there are lots of simulation tools/parameters that can affect the output accuracy.  Our solution is validated, thus I always push customer to follow our example until they have real data on their own boards before optimizing out too many capacitors.   

  • robert,

       tks for relpying. what is the TI recommending validating process for PDN? how can i come to the conclusion that the PDN performance is OK?

  • TI validates its PDN on the EVM by running a test to generate maximum load step.  The test is repeated across temperature and the voltage is slowly lowered until the system fails.  The voltage at which the system fails is then evaluated to ensure we have sufficient margin.  Customer could do something similar with their application.