AM3715: MCSPI3_SIMO Status during Idle Mode

Yume Lin

This is the correct behavior of the controller data output.  I do not see a way to force a H or L during an idle period. 

I am surprised that the signal remains mid-level with a pull-up enabled.  Are you sure it is enabled? 

Check the CONTROL_PADCONF register setting of the pin you are using for the SIMO signal.   Perhaps it has an opposite  pull enabled?

--Paul 

Hi Paul,

Thanks for feedback.

This symptom is the same when we set the SIMO with pull up configuration, but its skew rate will be faster to mid-level.

According to SPI standard, SIMO will keep the high or low level during idle depending on the last bit data before enter idle state.

I am wondering how SIMO keep high level when the last bit data is "1" if it is Hi-Z during idle state.

I think it need be output during data transfer, even idle state, right?

BR,

Yume

Still strange that the signal settles at mid-level.   It should ramp to  a logic 1 if both pulls (ASIC and PADCONF) are set high.

The Hi-Z output is the correct operation for this device and the pull should have worked.   Is there anything else connected that could be driving the signal?    What happens if you disable both pull-ups? 

--Paul 

Hi Paul,

Mid-level is related to idle period time, Hi-Z output need more time to ramp up to logic 1 by pull-up.

Please refer to below waveform of MCSPI2 which we use for touch controller, it operates at slower speed and have longer idle time.

You can observe the signal slowly ramp up when last bit data is 0 if pull-up (~2K Ohm) and slowly ramp down when last bit data is 1 if no pull.

* Ramp up when last bit data is 0 if pull-up

* Ramp down when last bit data is 1 if no pull

BR, Yume

Yume

So the signal is behaving as expected. Ensure the pull is enabled.

  -  Paul 

Hi Paul,

When SIMO be Hi-Z output, its ramp up voltage will depend on idle time.

If time is enough, it will ramp up to logic "1", but if time is too short, it will ramp up to mid-level.

Could we control the idle time?

Or have any chance to modify SIMO to be output (high or low follow the last bit data) during idle?

BR, Yume

Yume Lin said:

When SIMO be Hi-Z output, its ramp up voltage will depend on idle time.

If time is enough, it will ramp up to logic "1", but if time is too short, it will ramp up to mid-level.

The scope shot you provided earlier, "Ramp up when last bit data is 0 if pull-up", shows that the ramp time to be ~0.5 clk cycle, or ~250nS(?).  The delay between words only appears to be 3-4 clock cycles.  In this scope shot, the SPI output never seems to settle at mid point, rather passes through it.

Under what scenario do you see it settle at mid point?  

Yume Lin said:

Or have any chance to modify SIMO to be output (high or low follow the last bit data) during idle?

There is no control for this. 

--Paul 

Hi Paul,

Under what scenario do you see it settle at mid point? 

--> Please see the waveform of MCSPI3_CLK and MCSPI3_SIMO used for FPGA upload firmware. (First Fig.)

When the SPI speed up to 24MHz/ 48MHz, the idle time between 8-bits data is possible to be less than 200ns.

And SIMO is possible to ramp up to mid-level.

BR, Yume

Looks like the first waveform, during idle, reaches ~1v before the next word is transmitted. Is this an issue for the FPGA?

The solution would be to use a stronger Pull to increase the speed of the edge.

Hi Paul,

Agree stronger Pull would be workaround solution.

But why SIMO signal be Hi-Z output during idle?

My understanding is SIMO should be output H or L depending on the last bit data before enter idle state.

BR, Yume

I am not aware why this approach was taken on this device.