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[FAQ] AM625: jtag schematics to implement in customer board

Part Number: AM625
Other Parts Discussed in Thread: SK-AM62

Hi everybody , 

customer  would like to have Jtag connections/capabilities on  their  production  board .

I suggested  to copy  SK-AM62    but here are questions :  

- do you need to implement  just page 29  ( so jtag connector )  ?   coudl you avoid  onboard  clock buffer ( to save money ) ?

- is page 28  ( all buffers  )  needed at all ?

- do you need if using 5V from PC  the   do we must pull USB_VBUS pin to 1.8V?

please consider they are going to use XDS110  on their production board 

I also suggested  schematics  as on web here https://dev.ti.com/tirex/explore/node?node=AOi9Jj0vmBMJ0KQKaKITgg__FUz-xrs__LATEST   

but not 100% crystla clean what to do  

thank you very much 

BR
Carlo

PS  here you have  page 28 & 29  of SK-AM62  schematics  I m referring to ( page 28 is the one w the buffers )

  • It is not clear if your customer plans to include the on-board XDS110 debugger in their product design or do they only plan to connect an external debugger when it is needed?

    They will not need any of the XDS110 debugger or buffer circuits when only connecting the JTAG signals to a connector which will connect to a external debugger.

    Regards,
    Paul

  • Hi Paul 

    No XDS110 on their board 

    they need a proper connector w proper connection. So to be able to plug an external emulator

    could you kindly confirm proper schematics they should implement?

    It is page 29 of sk/am62. As shared ?

    do you have a schematics to share ?

    thank you

    br 

    carlo

  • They should connect TMS, TDI, TDO, TCK, EMU0, and EMU1 from the connector directly to the AM62x device with separate external pull-ups on each of these signals.

    They should connect TRSTn from the connector directly to the AM62x device with an external pull-down on this signal.

    They will need to research the debugger expectation for the RTCK connection. Some debuggers may require a RTCK, while others have a configurable option to use it or ignore it. I have seen people simply loop TCK back to RTCK near the connector, but this can cause signal integrity issues. Splitting a signal trace like this can cause reflections that can introduce clock glitches. I suggest placing two resistors near the TCK connector pin and inserting one in series with the TCK signal connecting to the AM62x device and the other in series with the RTCK path when TCK is looped back to RTCK. This acts like series terminations and the resistor values can be adjusted to impedance match the signal transition into two paths which also attenuates any undesired reflections.

    The supply connected to the debugger connector should be the same supply that is connected to IO power rail of the AM62x JTAG IOs (VDDSHV_MCU).

    They should also reference the following document: Emulation and Trace Headers

    Regards,
    Paul

           

  • Hi Paul 

    I m passing the ccustomer and give you feedbacks

    thank you veyr much

    BR

    Carlo

  • Hi Paul 

    customer  collected your info and is going to do the schematics hereunder  ( as out of SK-AM62 ) : is it correct  ?   anything to modify ? any suggestion ?

    (please conisder thier goal is to be able to use external XDS110 for debug etc connecting to their connector onboard  ) 

    coudl you kindly also elaborate this point :    wheter  the software affects JTAG?

    here is schematics  they are willing to implement :  

    thank you 

    BR
    Carlo

  • I already told you what needs to be done to connect the JTAG signals between the connector and the AM62x device.

    The schematic snapshots from the SK-AM62 does not include all of the external pull resistors which were mentioned in my previous replay. It also includes things that are not necessary like the SEL_XDS110_INV signal. 

    The TCK and RTCK clock paths can be buffered to ensure there is no signal integrity issues due to the signal split, but they do not need two input devices with the SEL_XDS110_INV signal. They also need to understand the clock buffers will improve signal integrity, but they will also insert delay which will reduce the maximum operating speed of the JTAG interface. So using clock buffers is a safe approach, but has a cost. The actual cost of the devices and the reduction of JTAG operating speed. This is a system level design trade-off, where they need to decide which is the better option for their product. They could potentially design their PCB to accommodate either option based on the components installed. For example, route each path through both a buffer footprint and a resistor footprint connected in parallel. This would allow them to install the buffer or the resistor to see which works best for them.

    Regards,
    Paul

  • HI Paul 

    so please  to be on the same page   here is what I understood ( coudl you kindly help me on what is missing considering they will plug XDS110  as external emulator :

    N1  -They should connect TMS, TDI, TDO, TCK, EMU0, and EMU1 from the connector directly to the AM62x device with separate external pull-ups on each of these signals.

    N2 -They should connect TRSTn from the connector directly to the AM62x device with an external pull-down on this signal.

    N3   TCK & RTCK can be shorted  ( XDS110 not fastest emulator  so integrity should be fine ) 

    please I m  missing   signals  ------ RSTN ,  TDIS ,  SELXDS110      what shoudl they do on these ?

    we are trying to win the customer and Jtag connection must be working  first shot 

    thank you veyr mcuh 

    BR

    Carlo

  • N1 - correct.

    N2 - correct.

    N3 - reflections from a split signal trace can cause a signal to glitch if the reflection creates a non-monotonic transition that occurs near the input buffer switching threshold. Glitches on a clock are very bad. This could cause the JTAG state machine to lock-up or do unpredictable things. This type of signal reflection issue is completely independent of speed. It could occur even if the clock signal is only operating at 1Hz because the reflection is the result of a signal transition. They should insert buffers in each of the split signal paths if they do not want to perform signal integrity analysis of their PCB to understand if the simple two series termination resistor approach will work.

    The RSTN signal is optional output reset from the debugger.  It simply provides a way for the debugger to initiate a cold reset when ANDed with the other device reset sources.  This signal may be an open-drain output from the debugger, which means it needs to be pulled high with an external 4.7K pull-up.

    The JTAG connector pin connected to the SEL_XDS110_INV signal was originally defined to be another ground and the SK-AM62 designer disconnected it from ground and used as a detect signal to know when an external debugger was connected.  Please refer to the "TI 20-Pin CTI Header Signal Naming Convention" table in the "Emulation and Trace Headers" application note mention in my previous reply.  This is the best reference for JTAG connector pinout details.  This document will help you understand all of the signals you are asking about.

    Regards,
    Paul

  • Hi Paul 

    thank you very much 

    I summarized all your inputs and share customemr ,  I ll give you feedback asap  

    BR

    Carlo