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[FAQ] TDA4VM: How to read the DDR frequency from Linux

Part Number: TDA4VM
Other Parts Discussed in Thread: DRA821

The DDR is configured by R5 SPL/SBL. Is there a way to check the frequency of DDR from Linux at runtime?

  • The DDR frequency can be determined runtime from Linux/QNX making use of the k3conf application from Linux userspace.

    For J721e/TDA4VM the below command will give the DDR_PLL clock frequency:

    k3conf dump clock 47

    |---------------------------------------------------------------------------------------|
    | Device ID | Clock ID | Clock Name | Status | Clock Frequency |
    |---------------------------------------------------------------------------------------|
    | 47 | 0 | DEV_DDR0_DDRSS_VBUS_CLK | CLK_STATE_READY | 1000000000 |
    | 47 | 1 | DEV_DDR0_PLL_CTRL_CLK | CLK_STATE_READY | 500000000 |
    | 47 | 2 | DEV_DDR0_DDRSS_DDR_PLL_CLK | CLK_STATE_READY | 1066500000 |
    | 47 | 3 | DEV_DDR0_DDRSS_CFG_CLK | CLK_STATE_READY | 125000000 |
    | 47 | 4 | DEV_DDR0_DDRSS_IO_CK_N | CLK_STATE_READY | 0 |
    | 47 | 5 | DEV_DDR0_DDRSS_IO_CK | CLK_STATE_READY | 0 |
    |---------------------------------------------------------------------------------------|

    The number 47 is the Device ID for DDR as per: https://software-dl.ti.com/tisci/esd/latest/5_soc_doc/j721e/devices.html

    From the output we get the DDR_PLL_CLK frequency - The clock_ID 2 in the list.

    | 47 | 2 | DEV_DDR0_DDRSS_DDR_PLL_CLK | CLK_STATE_READY | 1066500000 |

    The frequency above is 1066500000 Hz.
    The frequency of DDR is 1066500000 * 4 = 4266 MTS
    (Mega Transfers per Second).

    Similarly for DRA821https://software-dl.ti.com/tisci/esd/latest/5_soc_doc/j7200/devices.html

    The device_ID for DDR is 8. So the command will be:

    k3conf dump clock 8

    Similarly for the other TDA4 class of devices the above method can be used.

    Best Regards,
    Keerthy