"AM62x DDR Board Design and Layout Guidelines" that:
for the processor’s DDR PHY interface.
This thread has been locked.
If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.
Hello Ryan Jiang
Thank you for the query.
Can you please share the use case.
For the propagation delay, the delay here is only for the DDR/LPDDR traces on the board. We don’t need to include any package level propagation delay.
Regards,
Sreenivasa
HI Kallikuppa ,
I am routing the LPDDR4 with AM623x.
So in the case of AM623x with LPDDR4, as long as I match the trace delay and LPDDR4 side on package delay, it should work, the TI's AM623x on package delay does not need to be included?
Regards,
Ryan Jiang
Hello Ryan Jiang
Thank you for the note and your understanding is correct. Please ensure you follow the below guide.
https://www.ti.com/lit/an/sprad06/sprad06.pdf
Regards,
Sreenivasa