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AM5749: Back-to-back read issue

Part Number: AM5749


I interfaced an FPGA to the SoC via GPMC.

The retained configuration is:

  • Asynchronous
  • 16 bits
  • and CYCLE2CYCLE = 0

Despite this, I observe a very long pause between two consecutive readings.

The registers content is as below:

GPMC_CONFIG1_i = 0x40C11000

GPMC_CONFIG2_i = 0x00121200

GPMC_CONFIG3_i = 0x00000000

GPMC_CONFIG4_i = 0x12001200

GPMC_CONFIG5_i = 0x000F1515

GPMC_CONFIG6_i = 0x80000000

GPMC_CONFIG7_i = 0x00000F52

Is something in my settings that could explain this long delay?

The read transaction is performed through a memcpy (no DMA at the moment).