AM5748: EDMA between FPGA (over GPMC) and DSP L2 memory issue

Steve MULLER

Part Number: AM5748

Hi,

I designed a system where an FPGA is connected to the Soc via the GPMC.

I am able to exchange data between the DSP L2 memory and the FPGA using the DSP.

I am also able to exchange data between the FPGA and the FPGA using EDMA.

However, I am not able to exchange data between the DSP L2 memory and the FPGA using EDMA:

I suppose something is wrong in my configuration. Could someone give me some clues?

Kind regards,

Steve

+1 Stanley Liu over 1 year ago

Hi,

Are you using DSP EDMA or SYSTEM EDMA?

What address range do you program EDMA when accessing DSP L2 memory?

If accessing DSP L2 memory via SYSTEM EDMA, the address is 0x4080_0000 ~ 0x4084_7FFF.

If accessing DSP L2 memory via DSP EDMA, the address is 0x0080_0000 ~ 0x0084_7FFF.

After EDMA writes to L2 memory, DSP has to invalidate L1 cache before reading from L2 memory.

Before EDMA moves data out of L2 memory, DSP has to writeback data from L1 cache to L2 memory.

Regards,
Stanley

0 Steve MULLER over 1 year ago in reply to Stanley Liu

Hi Stanley,

This hint has solved the problem.

Another question, are there primitives to force writeback and invalide the cache ?

Kind regards,

Steve

+1 Stanley Liu over 1 year ago in reply to Steve MULLER

Please refer to RTOS SDK available at the below link.

You can refer to CSL in PDK from RTOS SDK.

CSL includes bare metal cache operation code.

Another option is if you are running TI-RTOS on DSP, TI-RTOS also provides Cache APIs.

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