This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

OMAP-L138: Problem with ARM/DSP DMA

Part Number: OMAP-L138

Team,

The system I am working on is built around an OMAP-L138 with DSP where we have programmed both the ARM core and the DSP.

The ARM uses UART1 and SPI0 for communication while the DSP uses SPI1. All of these interfaces use DMA.

 If (and only if) we enable the DSP SPI we get very strange errors that typically affect any communication interface on the ARM, e.g. corrupt data in the ARM UART or SPI communication or errors in the HPI interface.

The errors do not seem to occur if we implement the DSP SPI communication purely interrupt-based, without DMA.

Since these errors only occur when the DMA-controlled DSP communication is enabled I suspect the DSP DMA access to be at fault here.

 Now my question is, can you think of any reason why the DSP DMA would corrupt communication interfaces used by the ARM or, as a more general question, are there any specific recommendations or guidelines that we should follow in our implementation when ARM and DSP both use DMA?

Are there any typical pitfalls you can think of when ARM and DSP concurrently use DMA?

 We do use shadow regions where possible to access DMA configuration on both cores.

 Here is some additional information regarding our implementation:

 ARM:

 

SPI0 via EDMA3 Channel Controller 0, Transfer Controller 1

Configuration and Interrupt completion check via Shadow Region 0

RX: Event 14 / SPI0 Receive

TX: Event 15 / SPI0 Transmit

Transfer Completion Interrupt: EDMA3_0_CC0_INT0 (AINTC Number 11)

 

UART1 via EDMA3 Channel Controller 0, Transfer Controller 1

Configuration and Interrupt completion check via Shadow Region 0

RX: Event 12 / UART1 Receive

TX: Event 13 / UART1 Transmit

Transfer Completion Interrupt: EDMA3_0_CC0_INT0 (AINTC Number 11)

 

DSP:

 

SPI1 via EDMA3 Channel Controller 0, Transfer Controller 0

Configuration and Interrupt completion check via Shadow Region 1

RX: Event 18 / SPI1 Receive

TX: Event 19 / SPI1 Transmit

Transfer Completion Interrupt: EDMA3_0_CC0_INT1 (DSPINTC Number 8)

Error Interrupt: EDMA3_0_CC0_ERRINT (DSPINTC Number 56)

 I can provide you with more of our actual source code at any time, if necessary.

 It would be great if you could help us find out what’s going wrong here. Thank you very much in advance.

Also please do not hesitate to contact me if you need more information regarding our implementation.