From Table 6-1 in the AM65xx datasheet (Pin Attributes) we see most pins are "HI-Z" at RESET.
I am supporting an application where the GPMC address pins (GPMC0_A**) are connected to MRAM; they are not PU/PD externally.
The terminology from Table 6-1 is that "Ball Reset State" is "OFF" which = Hi-Z
Also, it looks like after RESET they default to GPIO (Hi-Z) and have to be reconfigured.
What we are really wondering here is if external noise when they are Hi-Z could be causing latch-up on these pins?
Do these pins really go to HI-Z at RESET?
Is there no requirement for external PU/PD resistors in this case?
(How about termination for unused GPIO ("OFF") pins?)