SMOMAPL138B-HIREL: UPP with Independent TX and RX data lines

vetrivel M

Part Number: SMOMAPL138B-HIREL
Other Parts Discussed in Thread: OMAPL138

HI Team,

we have designed custom board with OMAPL138 and FPGA where both are connected via UPP interface.
Both DSP and FPGA needs to send and receive 16bit or 8 Bit data and planning to use in DUPLEX 1 mode, where CH-A transmits and CH-B receives in DSP.

We have the following queries regarding the UPP communication,

1. Is it possible to communicate with FPGA and DSP simulatenously. I assume UPP control siganls are independent (WAIT, START, ENABLE and CLOCK), hence we will not face issue on these signals.
But for data can we split the 16 bit data lines to dedicate 8 bit each for FPGA and DSP Transmission??

over 3 years ago

0 Kallikuppa Sreenivasa over 3 years ago

TI__Guru**** 214540 points

Hello vetrivel,

Thank you for the query.

Is there a block diagram that explains the connections.

Can you provide some explanation on the development environment you are using.

Regards,

Sreenivasa

0 vetrivel M over 3 years ago

Prodigy 150 points

Hi Kallikuppa Sreenivasa,

Thanks for the response.

Hope you understood my problem. I am able to transmit and receive data via UPP. But after receiving if i am accessing the memory then that memory section (size of DMA burst) is not filled in the successive receive cycles. For clarification i am ready to have quick call with you as well.

Herewith i am attaching diagram explaining UPP signals connection of DSP and FPGA.

IDE : CCS9.3.0.00012
SDK : ti-processor-sdk-rtos-omapl138-lcdk-06.03.00.106

Regards,

Vetri

0 vetrivel M over 3 years ago in reply to vetrivel M

Prodigy 150 points

Attaching the diagram

0 vetrivel M over 3 years ago in reply to vetrivel M

Prodigy 150 points

Hi Kallikuppa Sreenivasa,

Skip the last response, posted the wrong response in this query by mistake.

Please find the requested details,

Herewith i am attaching diagram explaining UPP signals connection of DSP and FPGA.

Development Details :

IDE : CCS9.3.0.00012
SDK : ti-processor-sdk-rtos-omapl138-lcdk-06.03.00.106

Regards,

Vetri

0 Kallikuppa Sreenivasa over 3 years ago in reply to vetrivel M

TI__Guru**** 214540 points

Hello Vetri

Thank you.

Can you please elaborate the query with reference to the block diagram.

1. Is it possible to communicate with FPGA and DSP simulatenously. I assume UPP control siganls are independent (WAIT, START, ENABLE and CLOCK), hence we will not face issue on these signals.

But for data can we split the 16 bit data lines to dedicate 8 bit each for FPGA and DSP Transmission??

Are you looking to enable both interface together and send data over the 16 bit interface?

Regards,

Sreenivasa

0 vetrivel M over 3 years ago in reply to Kallikuppa Sreenivasa

Prodigy 150 points

Hi sreenivasa,

Yes, we would like to do transmit and receive 8bit data using the two UPP channels with the FPGA simultaneously.

can we configure the CH A of UPP to use the data Line [0:7] for transmit and CH B of UPP to use data Line [8:15] for Receive?

Is so please let me know to configure that.

0 Kallikuppa Sreenivasa over 3 years ago in reply to vetrivel M

TI__Guru**** 214540 points

Hello Vetrivel,

Thank you for the inputs.

Let me check if this is feasible.

Please expect delay in response due to yearend holidays.

Regards,

Sreenivasa

0 Kallikuppa Sreenivasa over 3 years ago in reply to Kallikuppa Sreenivasa

TI__Guru**** 214540 points

Hello Vetrivel,

I received some inputs internally that i am sharing.

Please note that the attached analysis is provided to support your query and needs to be validated by you to confirm this would work.

omap-L138_UPP.docx

Regards,

Sreenivasa

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SMOMAPL138B-HIREL: UPP with Independent TX and RX data lines