TMDSEVM6678: SPI NOR FLASH TEST

Thilak Ram

Part Number: TMDSEVM6678

Hi,

I am working in the 6678 eval Card. I am testing the SPI NOR Flash using platform util test code and adding debug prints in it .I am getting the verification error .

I have attached the error image and the place where the error gets identified.Error Function: Platform device write .In that pBlock and pPage function gets error indication

#define PLATFORM_ERRNO_OOM 0x00000030 /**< Out of memory.. tried to allocate RAM but could not.

I am getting this error.Please check and suggest.

Regards,

Thilak

over 1 year ago

0 Shankari G over 1 year ago

TI__Mastermind 25095 points

Thilak,

By any chance, you looked into the following FAQs and it's steps ? on How to run the platform test on C6678 EVM.

Platform test:

[FAQ] TMS320C6678: How to build and run the platform test on C6678 EVM ? - Processors forum - Processors - TI E2E support forums

Startup guide:

[FAQ] TMS320C6678: Quick set up Guide C6678 and C6678-EVM - Processors forum - Processors - TI E2E support forums

---

Please post your complete output logs on the gel-output and the platform test-output.

Regards

Shankari G

0 Thilak Ram over 1 year ago in reply to Shankari G

Intellectual 470 points

spi nor flash data.txt

IBL: Booting from NOR
IBL: Booting from NOR
IBL: Booting from NOR
IBL: Booting from NOR
IBL: Booting from NOR
IBL: Booting from NOR
IBL: Booting from NOR
IBL: Booting from NOR
IBL: Booting from NOR
IBL: Booting from NOR
IBL: Booting from NOR
IBL: Booting from NOR
IBL: Booting from NOR
IBL: Booting from NOR
IBL: Booting from NOR
IBL: Booting from NOR
IBL: Booting from NOR
IBL: Booting from NOR
IBL: Booting from NOR
IBL: Booting from NOR
IBL: Booting from NOR
IBL: Booting from NOR
IBL: Booting from NOR
IBL: Booting from NOR
IBL: Booting from NOR
IBL: Booting from NOR
IBL: Booting from NOR
IBL: Booting from NOR
IBL: Booting from NOR
IBL: Booting from NOR
IBL: Booting from NOR
IBL: Booting from NOR
IBL: Booting from NOR
IBL: Booting from NOR
IBL: Booting from NOR
IBL: Booting from NOR
IBL: Booting from NOR
IBL: Booting from NOR
IBL: Booting from NOR
IBL: Booting from NOR
IBL: Booting from NOR
IBL: Booting from NOR
IBL: Booting from NOR
IBL: Booting from NOR
IBL: Booting from NOR
IBL: Booting from NOR
IBL: Booting from NOR
IBL: Booting from NOR
IBL: Booting from NOR
IBL: Booting from NOR
IBL: Booting from NOR
IBL: Booting from NOR
IBL: Booting from NOR
IBL: Booting from NOR
IBL: Booting from NOR
IBL: Booting from NOR
IBL: Booting from NOR
IBL: Booting from NOR
IBL: Booting from NOR
IBL: Booting from NOR
IBL: Booting from NOR
IBL: Booting from NOR
IBL: Booting from NOR
IBL: Booting from NOR
IBL: Booting from NOR
IBL: Booting from NOR
IBL: Booting from NOR
IBL: Booting from NOR
IBL: Booting from NOR
IBL: Booting from NOR
IBL: Booting from NOR
IBL: Booting from NOR
IBL: Booting from NOR
IBL: Booting from NOR
IBL: Booting from NOR
IBL: Booting from NOR
IBL: Boplatform_device_open(deviceid=0x50,flags=0x0) called
p_info->version = 2.00.00.15
p_info->cpu.core_count  = 8
p_info->cpu.name        = TMS320C6678
p_info->cpu.id  = 21
p_info->cpu.revision_id = 0
p_info->cpu.silicon_revision_major      = 0
p_info->cpu.silicon_revision_minor      = 0
p_info->cpu.megamodule_revision_major   = 8
p_info->cpu.megamodule_revision_minor   = 1
p_info->cpu.endian      = 1
p_info->board_name      = TMDXEVM6678L
p_info->frequency       = 1000
p_info->board_rev       = 14
p_info->led[PLATFORM_USER_LED_CLASS].count      = 4
p_info->led[PLATFORM_SYSTEM_LED_CLASS].count    = 0
p_info->emac.port_count = 2
EMAC port 1 connected to the PHY.
MAC Address = 10:ce:a9:c0:a0:e7
platform_device_open(deviceid=0xbb18,flags=0x0) called

NOR Device:
p_device->device_id     = 47896
p_device->manufacturer_id       = 32
p_device->width = 8
p_device->block_count   = 256
p_device->page_count    = 256
p_device->page_size     = 256
p_device->spare_size    = 0
p_device->handle        = 47896
p_device->flags = 0
p_device->bboffset      = 0
NOR test start:1
platform_device_open(deviceid=0xbb18,flags=0x0) called
BUF_ORIG:255,no-0
BUF_ORIG:255,no-1
BUF_ORIG:255,no-2
BUF_ORIG:255,no-3
BUF_ORIG:255,no-4
BUF_ORIG:255,no-5
BUF_ORIG:255,no-6
BUF_ORIG:255,no-7
BUF_ORIG:255,no-8
BUF_ORIG:255,no-9
BUF_ORIG:255,no-10
BUF_ORIG:255,no-11
BUF_ORIG:255,no-12
BUF_ORIG:255,no-13
BUF_ORIG:255,no-14
BUF_ORIG:255,no-15
BUF_ORIG:255,no-16
BUF_ORIG:255,no-17
BUF_ORIG:255,no-18
BUF_ORIG:255,no-19
BUF_ORIG:255,no-20
BUF_ORIG:255,no-21
BUF_ORIG:255,no-22
BUF_ORIG:255,no-23
BUF_ORIG:255,no-24
BUF_ORIG:255,no-25
BUF_ORIG:255,no-26
BUF_ORIG:255,no-27
BUF_ORIG:255,no-28
BUF_ORIG:255,no-29
BUF_ORIG:255,no-30
BUF_ORIG:255,no-31
BUF_ORIG:255,no-32
BUF_ORIG:255,no-33
BUF_ORIG:255,no-34
BUF_ORIG:255,no-35
BUF_ORIG:255,no-36
BUF_ORIG:255,no-37
BUF_ORIG:255,no-38
BUF_ORIG:255,no-39
BUF_ORIG:255,no-40
BUF_ORIG:255,no-41
BUF_ORIG:255,no-42
BUF_ORIG:255,no-43
BUF_ORIG:255,no-44
BUF_ORIG:255,no-45
BUF_ORIG:255,no-46
BUF_ORIG:255,no-47
BUF_ORIG:255,no-48
BUF_ORIG:255,no-49
BUF_ORIG:255,no-50
BUF_ORIG:255,no-51
BUF_ORIG:255,no-52
BUF_ORIG:255,no-53
BUF_ORIG:255,no-54
BUF_ORIG:255,no-55
BUF_ORIG:255,no-56
BUF_ORIG:255,no-57
BUF_ORIG:255,no-58
BUF_ORIG:255,no-59
BUF_ORIG:255,no-60
BUF_ORIG:255,no-61
BUF_ORIG:255,no-62
BUF_ORIG:255,no-63
BUF_1:255,no-0
BUF_1:255,no-1
BUF_1:255,no-2
BUF_1:255,no-3
BUF_1:255,no-4
BUF_1:255,no-5
BUF_1:255,no-6
BUF_1:255,no-7
BUF_1:255,no-8
BUF_1:255,no-9
BUF_1:255,no-10
BUF_1:255,no-11
BUF_1:255,no-12
BUF_1:255,no-13
BUF_1:255,no-14
BUF_1:255,no-15
BUF_1:255,no-16
BUF_1:255,no-17
BUF_1:255,no-18
BUF_1:255,no-19
BUF_1:255,no-20
BUF_1:255,no-21
BUF_1:255,no-22
BUF_1:255,no-23
BUF_1:255,no-24
BUF_1:255,no-25
BUF_1:255,no-26
BUF_1:255,no-27
BUF_1:255,no-28
BUF_1:255,no-29
BUF_1:255,no-30
BUF_1:255,no-31
BUF_1:255,no-32
BUF_1:255,no-33
BUF_1:255,no-34
BUF_1:255,no-35
BUF_1:255,no-36
BUF_1:255,no-37
BUF_1:255,no-38
BUF_1:255,no-39
BUF_1:255,no-40
BUF_1:255,no-41
BUF_1:255,no-42
BUF_1:255,no-43
BUF_1:255,no-44
BUF_1:255,no-45
BUF_1:255,no-46
BUF_1:255,no-47
BUF_1:255,no-48
BUF_1:255,no-49
BUF_1:255,no-50
BUF_1:255,no-51
BUF_1:255,no-52
BUF_1:255,no-53
BUF_1:255,no-54
BUF_1:255,no-55
BUF_1:255,no-56
BUF_1:255,no-57
BUF_1:255,no-58
BUF_1:255,no-59
BUF_1:255,no-60
BUF_1:255,no-61
BUF_1:255,no-62
BUF_1:255,no-63
test_nor: Write test data failed errno = 0x30
BUF_0:171,no-0
BUF_0:171,no-1
BUF_0:171,no-2
BUF_0:171,no-3
BUF_0:171,no-4
BUF_0:171,no-5
BUF_0:171,no-6
BUF_0:171,no-7
BUF_0:171,no-8
BUF_0:171,no-9
BUF_0:171,no-10
BUF_0:171,no-11
BUF_0:171,no-12
BUF_0:171,no-13
BUF_0:171,no-14
BUF_0:171,no-15
BUF_0:171,no-16
BUF_0:171,no-17
BUF_0:171,no-18
BUF_0:171,no-19
BUF_0:171,no-20
BUF_0:171,no-21
BUF_0:171,no-22
BUF_0:171,no-23
BUF_0:171,no-24
BUF_0:171,no-25
BUF_0:171,no-26
BUF_0:171,no-27
BUF_0:171,no-28
BUF_0:171,no-29
BUF_0:171,no-30
BUF_0:171,no-31
BUF_0:171,no-32
BUF_0:171,no-33
BUF_0:171,no-34
BUF_0:171,no-35
BUF_0:171,no-36
BUF_0:171,no-37
BUF_0:171,no-38
BUF_0:171,no-39
BUF_0:171,no-40
BUF_0:171,no-41
BUF_0:171,no-42
BUF_0:171,no-43
BUF_0:171,no-44
BUF_0:171,no-45
BUF_0:171,no-46
BUF_0:171,no-47
BUF_0:171,no-48
BUF_0:171,no-49
BUF_0:171,no-50
BUF_0:171,no-51
BUF_0:171,no-52
BUF_0:171,no-53
BUF_0:171,no-54
BUF_0:171,no-55
BUF_0:171,no-56
BUF_0:171,no-57
BUF_0:171,no-58
BUF_0:171,no-59
BUF_0:171,no-60
BUF_0:171,no-61
BUF_0:171,no-62
BUF_0:171,no-63
BUF_1:255,no-0
BUF_1:255,no-1
BUF_1:255,no-2
BUF_1:255,no-3
BUF_1:255,no-4
BUF_1:255,no-5
BUF_1:255,no-6
BUF_1:255,no-7
BUF_1:255,no-8
BUF_1:255,no-9
BUF_1:255,no-10
BUF_1:255,no-11
BUF_1:255,no-12
BUF_1:255,no-13
BUF_1:255,no-14
BUF_1:255,no-15
BUF_1:255,no-16
BUF_1:255,no-17
BUF_1:255,no-18
BUF_1:255,no-19
BUF_1:255,no-20
BUF_1:255,no-21
BUF_1:255,no-22
BUF_1:255,no-23
BUF_1:255,no-24
BUF_1:255,no-25
BUF_1:255,no-26
BUF_1:255,no-27
BUF_1:255,no-28
BUF_1:255,no-29
BUF_1:255,no-30
BUF_1:255,no-31
BUF_1:255,no-32
BUF_1:255,no-33
BUF_1:255,no-34
BUF_1:255,no-35
BUF_1:255,no-36
BUF_1:255,no-37
BUF_1:255,no-38
BUF_1:255,no-39
BUF_1:255,no-40
BUF_1:255,no-41
BUF_1:255,no-42
BUF_1:255,no-43
BUF_1:255,no-44
BUF_1:255,no-45
BUF_1:255,no-46
BUF_1:255,no-47
BUF_1:255,no-48
BUF_1:255,no-49
BUF_1:255,no-50
BUF_1:255,no-51
BUF_1:255,no-52
BUF_1:255,no-53
BUF_1:255,no-54
BUF_1:255,no-55
BUF_1:255,no-56
BUF_1:255,no-57
BUF_1:255,no-58
BUF_1:255,no-59
BUF_1:255,no-60
BUF_1:255,no-61
BUF_1:255,no-62
BUF_1:255,no-63
test_nor: Data verification failed
test_nor: Write back original data failed errno = 0x30
NOR test complete:1

I have attached the log.I have only enabled test nor function.Also added debug prints for checking the buffer.Getting the error.writer buffer and read buffer is not the same.SPI NOR FLASH ISSUE.

NOTE:

I am able to successfully test the nand flash using emif in the card and i am able toget the debug prints.Please check and suggest

0 Shankari G over 1 year ago in reply to Thilak Ram

TI__Mastermind 25095 points

Thilak,

Please run the test in "NO-boot" mode and share the output console messages.

From your output messages, "IBL: Booting from NOR" ,this says, you are in "NOR-boot" mode.

Regards

Shankari G

0 Thilak Ram over 1 year ago in reply to Shankari G

Intellectual 470 points

Ok.Can you please send the no boot mode switch configuration .

0 Shankari G over 1 year ago in reply to Thilak Ram

TI__Mastermind 25095 points

Thilak,

Here you go..

In your C6678 EVM - board ----> You shall put the DIP Switch settings in "No boot mode" to connect to the CCS.

That is ------> DIP SW 3,4,5 and 6 like given below.

Please follow the steps sequentially given in this FAQ.

https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1082264/faq-tms320c6678-quick-set-up-guide-c6678-and-c6678-evm

Regards

Shankari G

0 Thilak Ram over 1 year ago in reply to Shankari G

Intellectual 470 points

[C66xx_0] Error in opening ../testconfig/platform_test_input.txt input file

I am getting this issue in no boot mode

0 Shankari G over 1 year ago in reply to Thilak Ram

TI__Mastermind 25095 points

Thilak,

Thilak Ram said:
[C66xx_0] Error in opening ../testconfig/platform_test_input.txt input file

This error indicates, ccs is looking for the file, "platform_test_input.txt" as a input file, which is supposed to be located at path : "C:\ti\pdk_c667x_2_0_16\packages\ti\platform\evmc6678l\platform_test\testconfig".

This file, "platform_test_input.txt" is missing in your PC to run the platform test.

Post the complete logs of the following

1. Test connection

2. Gel file

3. Platform test

Regards

Shankari G

0 Thilak Ram over 1 year ago in reply to Shankari G

Intellectual 470 points

Hi,

The same code when i changed into noboot mode and flashed after that only i get this error.

Whether in nor/nand boot mode i am getting the error logs.

0 Shankari G over 1 year ago in reply to Thilak Ram

TI__Mastermind 25095 points

Thilak,

Please try to follow all my instructions sequentially. So that it will be easy to understand the problem better to solve the issue.

When you are in "No-boot" mode and when you are flashing into NOR , if some errors occur, then.... that can also be a cause for your SPI-NOR test issue.

The NOR-writer flash utility works correctly for you ? Would you post the output console messages of NOr-writer utility??

So...

Please post the complete logs of the following in "No-boot" mode

1. Test connection

2. Gel file

3. Platform test

Then let us move to the NOR-boot mode...

Regards

Shankari G

0 Thilak Ram over 1 year ago in reply to Shankari G

Intellectual 470 points

Hi,

I have attached the gel output and test connection data of the platform test. Please check the attachment and let know.

Regards,

Thilak

jtag test connection.txt

This path-length test uses blocks of 64 32-bit words.

The test for the JTAG IR instruction path-length succeeded.
The JTAG IR instruction path-length is 6 bits.

The test for the JTAG DR bypass path-length succeeded.
The JTAG DR bypass path-length is 1 bits.

-----[Perform the Integrity scan-test on the JTAG IR]------------------------

This test will use blocks of 64 32-bit words.
This test will be applied just once.

Do a test using 0xFFFFFFFF.
Scan tests: 1, skipped: 0, failed: 0
Do a test using 0x00000000.
Scan tests: 2, skipped: 0, failed: 0
Do a test using 0xFE03E0E2.
Scan tests: 3, skipped: 0, failed: 0
Do a test using 0x01FC1F1D.
Scan tests: 4, skipped: 0, failed: 0
Do a test using 0x5533CCAA.
Scan tests: 5, skipped: 0, failed: 0
Do a test using 0xAACC3355.
Scan tests: 6, skipped: 0, failed: 0
All of the values were scanned correctly.

The JTAG IR Integrity scan-test has succeeded.

-----[Perform the Integrity scan-test on the JTAG DR]------------------------

This test will use blocks of 64 32-bit words.
This test will be applied just once.

Do a test using 0xFFFFFFFF.
Scan tests: 1, skipped: 0, failed: 0
Do a test using 0x00000000.
Scan tests: 2, skipped: 0, failed: 0
Do a test using 0xFE03E0E2.
Scan tests: 3, skipped: 0, failed: 0
Do a test using 0x01FC1F1D.
Scan tests: 4, skipped: 0, failed: 0
Do a test using 0x5533CCAA.
Scan tests: 5, skipped: 0, failed: 0
Do a test using 0xAACC3355.
Scan tests: 6, skipped: 0, failed: 0
All of the values were scanned correctly.

The JTAG DR Integrity scan-test has succeeded.

[End]

jtag test connection1.txt

-----[Measure the source and frequency of the final JTAG TCLKR input]--------

There is no hardware for measuring the JTAG TCLK frequency.

-----[Perform the standard path-length test on the JTAG IR and DR]-----------

This path-length test uses blocks of 64 32-bit words.

The test for the JTAG IR instruction path-length succeeded.
The JTAG IR instruction path-length is 6 bits.

The test for the JTAG DR bypass path-length succeeded.
The JTAG DR bypass path-length is 1 bits.

-----[Perform the Integrity scan-test on the JTAG IR]------------------------

This test will use blocks of 64 32-bit words.
This test will be applied just once.

Do a test using 0xFFFFFFFF.
Scan tests: 1, skipped: 0, failed: 0
Do a test using 0x00000000.
Scan tests: 2, skipped: 0, failed: 0
Do a test using 0xFE03E0E2.
Scan tests: 3, skipped: 0, failed: 0
Do a test using 0x01FC1F1D.
Scan tests: 4, skipped: 0, failed: 0
Do a test using 0x5533CCAA.
Scan tests: 5, skipped: 0, failed: 0
Do a test using 0xAACC3355.
Scan tests: 6, skipped: 0, failed: 0
All of the values were scanned correctly.

The JTAG IR Integrity scan-test has succeeded.

-----[Perform the Integrity scan-test on the JTAG DR]------------------------

This test will use blocks of 64 32-bit words.
This test will be applied just once.

Do a test using 0xFFFFFFFF.
Scan tests: 1, skipped: 0, failed: 0
Do a test using 0x00000000.
Scan tests: 2, skipped: 0, failed: 0
Do a test using 0xFE03E0E2.
Scan tests: 3, skipped: 0, failed: 0
Do a test using 0x01FC1F1D.
Scan tests: 4, skipped: 0, failed: 0
Do a test using 0x5533CCAA.
Scan tests: 5, skipped: 0, failed: 0
Do a test using 0xAACC3355.
Scan tests: 6, skipped: 0, failed: 0
All of the values were scanned correctly.

The JTAG DR Integrity scan-test has succeeded.

[End: Texas Instruments XDS100v1 USB Debug Probe_0]

gel output.txt

C66xx_0: GEL Output: Setup_Memory_Map...
C66xx_0: GEL Output: Setup_Memory_Map... Done.
C66xx_0: GEL Output: 
Connecting Target...
C66xx_0: GEL Output: DSP core #0
C66xx_0: GEL Output: C6678L GEL file Ver is 2.00500011 
C66xx_0: GEL Output: Global Default Setup...
C66xx_0: GEL Output: Setup Cache... 
C66xx_0: GEL Output: L1P = 32K   
C66xx_0: GEL Output: L1D = 32K   
C66xx_0: GEL Output: L2 = ALL SRAM   
C66xx_0: GEL Output: Setup Cache... Done.
C66xx_0: GEL Output: Main PLL (PLL1) Setup ... 
C66xx_0: GEL Output: PLL not in Bypass, Enable BYPASS in the PLL Controller... 
C66xx_0: GEL Output: PLL1 Setup for DSP @ 1000.0 MHz.
C66xx_0: GEL Output:            SYSCLK2 = 333.333344 MHz, SYSCLK5 = 200.0 MHz.
C66xx_0: GEL Output:            SYSCLK8 = 15.625 MHz.
C66xx_0: GEL Output:            SYSCLK7 = 166.666672 MHz.
C66xx_0: GEL Output: PLL1 Setup... Done.
C66xx_0: GEL Output: Power on all PSC modules and DSP domains... 
C66xx_0: GEL Output: Security Accelerator disabled!
C66xx_0: GEL Output: Power on all PSC modules and DSP domains... Done.
C66xx_0: GEL Output: PA PLL (PLL3) Setup ... 
C66xx_0: GEL Output: PA PLL Setup... Done.
C66xx_0: GEL Output: DDR3 PLL (PLL2) Setup ... 
C66xx_0: GEL Output: DDR3 PLL Setup... Done.
C66xx_0: GEL Output: DDR begin (1333 auto)
C66xx_0: GEL Output: XMC Setup ... Done 
C66xx_0: GEL Output: 
DDR3 initialization is complete.
C66xx_0: GEL Output: DDR done
C66xx_0: GEL Output: DDR3 memory test... Started
C66xx_0: GEL Output: DDR3 memory test... Passed
C66xx_0: GEL Output: PLL and DDR Initialization completed(0) ...
C66xx_0: GEL Output: configSGMIISerdes Setup... Begin
C66xx_0: GEL Output: 
SGMII SERDES has been configured.
C66xx_0: GEL Output: Enabling EDC ...
C66xx_0: GEL Output: L1P error detection logic is enabled.
C66xx_0: GEL Output: L2 error detection/correction logic is enabled.
C66xx_0: GEL Output: MSMC error detection/correction logic is enabled.
C66xx_0: GEL Output: Enabling EDC ...Done 
C66xx_0: GEL Output: Configuring CPSW ...
C66xx_0: GEL Output: Configuring CPSW ...Done 
C66xx_0: GEL Output: Global Default Setup... Done.
C66xx_0: GEL Output: Invalidate All Cache...
C66xx_0: GEL Output: Invalidate All Cache... Done.
C66xx_0: GEL Output: GEL Reset...
C66xx_0: GEL Output: GEL Reset... Done.

0 Shankari G over 1 year ago in reply to Thilak Ram

TI__Mastermind 25095 points

Thilak,

Yes, I verified your ourput messages of "Jtag-Test connection " and Gel output. It seems to be correct.

Next,

The third one, please post the output console messages of your platform test.

Particularly I would like to check the output messages of the NOR-test which is comprised inside the Platform test.

Regards

Shankari G

0 Thilak Ram over 1 year ago in reply to Shankari G

Intellectual 470 points

Hi,

I have posted earler too.Once again i am posting too .Pls check the console messages and suggest.

nor flash data.txt

NOR test start
platform_device_open(deviceid=0xbb18,flags=0x0) called 
test_nor: Write test data failed errno = 0x30
test_nor: Data verification failed
test_nor: Write back original data failed errno = 0x30
NOR test complete
NOR test start
platform_device_open(deviceid=0xbb18,flags=0x0) called 
test_nor: Write test data failed errno = 0x30
test_nor: Data verification failed
test_nor: Write back original data failed errno = 0x30
NOR test complete
NOR test start
platform_device_open(deviceid=0xbb18,flags=0x0) called 
test_nor: Write test data failed errno = 0x30
test_nor: Data verification failed
test_nor: Write back original data failed errno = 0x30
NOR test complete
NOR test start
platform_device_open(deviceid=0xbb18,flags=0x0) called 
test_nor: Write test data failed errno = 0x30
test_nor: Data verification failed
test_nor: Write back original data failed errno = 0x30
NOR test complete
NOR test start
platform_device_open(deviceid=0xbb18,flags=0x0) called 
test_nor: Write test data failed errno = 0x30
test_nor: Data verification failed
test_nor: Write back original data failed errno = 0x30
NOR test complete
NOR test start
platform_device_open(deviceid=0xbb18,flags=0x0) called 
test_nor: Write test data failed errno = 0x30
test_nor: Data verification failed
test_nor: Write back original data failed errno = 0x30
NOR test complete
NOR test start
platform_device_open(deviceid=0xbb18,flags=0x0) called 
test_nor: Write test data failed errno = 0x30
test_nor: Data verification failed
test_nor: Write back original data failed errno = 0x30
NOR test complete
NOR test start
platform_device_open(deviceid=0xbb18,flags=0x0) called 
test_nor: Write test data failed errno = 0x30
test_nor: Data verification failed
platform_device_open(deviceid=0x50,flags=0x0) called 
p_info->version	= 2.00.00.15
p_info->cpu.core_count	= 8
p_info->cpu.name	= TMS320C6678
p_info->cpu.id	= 21
p_info->cpu.revision_id	= 0
p_info->cpu.silicon_revision_major	= 0
p_info->cpu.silicon_revision_minor	= 0
p_info->cpu.megamodule_revision_major	= 8
p_info->cpu.megamodule_revision_minor	= 1
p_info->cpu.endian	= 1
p_info->board_name	= TMDXEVM6678L
p_info->frequency	= 1000
p_info->board_rev	= 14
p_info->led[PLATFORM_USER_LED_CLASS].count	= 4
p_info->led[PLATFORM_SYSTEM_LED_CLASS].count	= 0
p_info->emac.port_count	= 2
EMAC port 1 connected to the PHY.
MAC Address = 10:ce:a9:c0:a0:e7
platform_device_open(deviceid=0xbb18,flags=0x0) called 

NOR Device: 
p_device->device_id	= 47896
p_device->manufacturer_id	= 32
p_device->width	= 8
p_device->block_count	= 256
p_device->page_count	= 256
p_device->page_size	= 256
p_device->spare_size	= 0
p_device->handle	= 47896
p_device->flags	= 0
p_device->bboffset	= 0
NOR test start
platform_device_open(deviceid=0xbb18,flags=0x0) called 
test_nor: Write test data failed errno = 0x30
test_nor: Data verification failed
test_nor: Write back original data failed errno = 0x30
NOR test complete
NOR test start
platform_device_open(deviceid=0xbb18,flags=0x0) called 
test_nor: Write test data failed errno = 0x30
test_nor: Data verification failed
test_nor: Write back original data failed errno = 0x30
NOR test complete
NOR test start
platform_device_open(deviceid=0xbb18,flags=0x0) called 
test_nor: Write test data failed errno = 0x30
test_nor: Data verification failed
test_nor: Write back original data failed errno = 0x30
NOR test complete

Nor test data

0 Shankari G over 1 year ago in reply to Thilak Ram

TI__Mastermind 25095 points

Thilak Ram,

In your earlier posts, you have uploaded the JTAG results twice.

This, is, what I did on the C6678 EVM ( Which I have in my hand )

1. Change the values as `1` in the "platform_test_input.txt" for test_nand and test_nor, located at C:\ti\pdk_c667x_2_0_16\packages\ti\platform\evmc6678l\platform_test\testconfig\platform_test_input.txt

init_pll = 1
init_ddr = 1
init_uart = 1
init_tcsl = 1
init_phy = 1
init_ecc = 1

print_info = 1
print_current_core_id = 1
print_switch_state = 1
test_eeprom = 1
test_nand = 1
test_nor = 1
test_led = 1
test_uart = 1
run_external_memory_test = 1
run_internal_memory_test = 1

init_config_pll1_pllm = 0
init_config_uart_baudrate = 115200

nand_test_block_number = 1000
nor_test_sector_number = 10
led_test_loop_count = 1
led_test_loop_delay = 2000000
ext_mem_test_base_addr = 0x80000000
ext_mem_test_length = 0x1fffffff
int_mem_test_core_id = 2

=====

For me, I received the following console output messages:

============================================

[C66xx_0] p_info->version	= 2.00.00.15
p_info->cpu.core_count	= 8
p_info->cpu.name	= TMS320C6678
p_info->cpu.id	= 21
p_info->cpu.revision_id	= 0
p_info->cpu.silicon_revision_major	= 0
p_info->cpu.silicon_revision_minor	= 0
p_info->cpu.megamodule_revision_major	= 8
p_info->cpu.megamodule_revision_minor	= 1
p_info->cpu.endian	= 1
p_info->board_name	= TMDXEVM6678L
p_info->frequency	= 1000
p_info->board_rev	= 13
p_info->led[PLATFORM_USER_LED_CLASS].count	= 4
p_info->led[PLATFORM_SYSTEM_LED_CLASS].count	= 0
p_info->emac.port_count	= 2
EMAC port 1 connected to the PHY.
MAC Address = 40:5f:c2:b9:43:12

NAND Device: 
p_device->device_id	= 54
p_device->manufacturer_id	= 32
p_device->width	= 8
p_device->block_count	= 4096
p_device->page_count	= 32
p_device->page_size	= 512
p_device->spare_size	= 16
p_device->column	= 512
p_device->handle	= 8246
p_device->flags	= 0
p_device->bboffset	= 5
Bad Block Table (only bad block numbers shown): 
2538 

NOR Device: 
p_device->device_id	= 47896
p_device->manufacturer_id	= 32
p_device->width	= 8
p_device->block_count	= 256
p_device->page_count	= 256
p_device->page_size	= 256
p_device->spare_size	= 0
p_device->handle	= 47896
p_device->flags	= 0
p_device->bboffset	= 0

EEPROM Device (@ 0x50): 
p_device->device_id	= 80
p_device->manufacturer_id	= 1
p_device->width	= 8
p_device->block_count	= 1
p_device->page_count	= 1
p_device->page_size	= 65536
p_device->spare_size	= 0
p_device->handle	= 80
p_device->flags	= 0
p_device->bboffset	= 0

EEPROM Device (@ 0x51): 
p_device->device_id	= 81
p_device->manufacturer_id	= 1
p_device->width	= 8
p_device->block_count	= 1
p_device->page_count	= 1
p_device->page_size	= 65536
p_device->spare_size	= 0
p_device->handle	= 81
p_device->flags	= 0
p_device->bboffset	= 0
Current core id is 0
User switch 1 state is ON
UART test start
Open a serial port console in a PC connected to
the board using UART and set its baudrate to 115200
You should see following message --- 
This is a Platform UART API unit test ...
Type 10 characters in serial console
Char 0 = 1
Char 1 = 2
Char 2 = 3
Char 3 = 4
Char 4 = 5
Char 5 = 6
Char 6 = 7
Char 7 = 8
Char 8 = 9
Char 9 = 0
UART test complete
EEPROM test start
test_eeprom: passed
EEPROM test complete
NAND test start
test_nand: passed
NAND test complete
NOR test start
test_nor: passed
NOR test complete
LED test start
LED 0 ON
LED 0 OFF
LED 0 ON
LED 1 ON
LED 1 OFF
LED 1 ON
LED 2 ON
LED 2 OFF
LED 2 ON
LED 3 ON
LED 3 OFF
LED 3 ON
LED test complete
Internal memory test start
Internal memory test (for core 2) passed
Internal memory test complete
External memory test start
External memory test passed
External memory test complete
Test completed

There could be only two possibilities ( as the device open is successful in your log and it could fetch you the NOR related details---> which means the read() seems to be successful. Only the write () call gets failed....

============================

1. Some initilalization code might have got modified in your source.

Try this Remedy:

Re install the Processor SDK and follow the steps of the FAQs, again : [FAQ] TMS320C6678: How to build and run the platform test on C6678 EVM ? - Processors forum - Processors - TI E2E support forums

2. The NOR chip memory might have gone bad.

If have anyother C6678 spare board, try this test.

Alternative suggestion : --- You can try using the nor-utility and check.

=================

Try the NOR utility program, " norwriter_evm6657l.out " located at : C:\ti\pdk_c665x_2_0_16\packages\ti\boot\writer\nor\evmc6657l\bin.

Load this .out file and flash any sample app.out.

Follow the "step4" given at https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1057566/faq-tms320c6657-how-to-flash-the-ibl-intermediate-boot-loader-into-eeprom-and-how-to-flash-the-application-binary-into-nor-how-to-boot-the-ibl-application-binary

That is

Step 4 - Flashing app

1. The sample binary taken for this demonstration is UART_BasicExample_C6657_c66xTestProject.

2. Located at C:\ti\pdk_c665x_2_0_16\packages\MyExampleProjects\UART_BasicExample_C6657_c66xTestProject

3. Build and create the app binary using CCS 9.3

4. App binary, UART_BasicExample_C6657_c66xTestProject.out will be located at "C:\ti\pdk_c665x_2_0_16\packages\MyExampleProjects\UART_BasicExample_C6657_c66xTestProject\Debug\"

5. Flashing app binary into NOR-memory using NOR-writer.

Set your EVM to NO BOOT. Power on, launch target configuration in CCS, and connect to Core 0. Be sure the GEL file is used and DDR is initialized.
Copy the UART-app binary you want to flash to "C:\ti\pdk_c665x_2_0_16\packages\ti\boot\writer\nor\evmc6657l\bin" directory.
Rename the binary you copied in the previous step to “app.bin”.
In CCS, select Core 0 and open the Memory Browser
In the Memory Browser window, right click and select “Load Memory”
Load your app.bin to 0x80000000. Do so by selecting app.bin for the file, click Next, and input 0x80000000 for Start Address (Type-size selected should be 32-bit)
Load C:\ti\pdk_c665x_2_0_16\packages\ti\boot\writer\nor\evmc6657l\bin\norwriter_evm6657l.out
Run Core 0. This will program the flash memory.

If it succeeds, the console will print “NOR programming completed successfully”

Regards

Shankari G