Transmit timing requirement for UTOPIA Slave for TMS320C6415T

SRINIVASA RAO KILAPARTI

Other Parts Discussed in Thread: TMS320C6415T

Hi all,

I have couple of questions related to the UTOPIA transmit signals UXCLAV and UXSOC referring to the document SPRS226D--November 2003- Revised October 2004, page no:129, figure 59.

1) We have 8 DSPs in our module and the UXCLAV and UXSOC of the UTOPIA are connected to these 8 DSPs.

If UXADDR[4:0] is not available, how do the UXCLAV and UXSOC work?

2) What should be the state of these 2 signals so that we can send the data?

Thanks and regards,

Srinivasa Rao Kilaparti.

over 15 years ago

0 BrandonAzbell over 15 years ago

TI__Guru 63690 points

SRINIVASA RAO KILAPARTI said:

I have couple of questions related to the UTOPIA transmit signals UXCLAV and UXSOC.

If the device is not addressed, what will UXCLAV and UXSOC do? will they be in the tristate?

Is this a single PHY or Multi-PHY environment? The TMS320C64x DSP Universal Test and Operations PHY Interface for ATM (UTOPIA) RG (SPRU583) on the TMS320C6415T Product Folder indicates in Section 3.7 on page 18 that URCLAV, UXCLAV, UXSOC and UXDATA[7:0] are in a high-impedance state when the UTOPIA slave is not selected by the master.

0 SRINIVASA RAO KILAPARTI over 15 years ago in reply to BrandonAzbell

Prodigy 20 points

Hi Brandon,

This is a single PHY environment. The FPGA can choose any of the DSPs.

Thanks,

Srinivasa Rao Kilaparti

0 BrandonAzbell over 15 years ago in reply to SRINIVASA RAO KILAPARTI

TI__Guru 63690 points

Are you still implementing a polling routine on the Utopia Address lines to select the PHY to access?
How are your distinguishing between multiple DSPs on the Utopia bus?

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Transmit timing requirement for UTOPIA Slave for TMS320C6415T