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DRA829V-Q1: DRA829V-Q1

Goran Stojcevski
Prodigy 100 points
Part Number: DRA829V-Q1

Hi,

We are using a Central IO backplane communication(UART) for our product that has to be very stable and to have minimum impact of the A72(Linux system).

We are thinking of implementing the Central IO into the Main Domain R5F Cores.

Some questions:

How will Linux do a SW reset?
Can it be done by using SW_MCU_WARMRST?

    • Can Linux (A72) restart without affecting the Main Domain ethernet switch, CPSW9G?
    • Can Linux (A72) restart without affecting the Main Domain R5F cores?

We would like to have an IP link running when reseting the Linux(A72).

Can potential issues be mitigated by using the MCU_Domain R5F core and then using MAC2MAC IF?

Thank you for the support!

Best Regards
Goran

  • 0
    TI__Guru** 100755 points

    Hi Goran,


    Goran Stojcevski said:
    How will Linux do a SW reset?

    The present SDK implementation both U-Boot & Linux reset/reboot use the: https://software-dl.ti.com/tisci/esd/latest/2_tisci_msgs/pm/sysreset.html?highlight=tisci_msg_sys_reset

    Since the boot core is MCU_R5F the entire SoC aka main domain as well as the MCU domain is reset to start afresh.


    Goran Stojcevski said:
    Can Linux (A72) restart without affecting the Main Domain ethernet switch, CPSW9G?

    No. The current implementation resets the entire main domain which includes the ethernet switch.

    Goran Stojcevski said:
    Can Linux (A72) restart without affecting the Main Domain R5F cores?

    Like mentioned above the boot core is MCU_R5F so a reset should also trigger MCU_R5F reset to get control of R5 SPL without which
    Linux will not come up.

    Goran Stojcevski said:

    We would like to have an IP link running when reseting the Linux(A72).

    So your requirement is tot have ethernet Switch functional across Linux(A72) reset?

    - Keerthy

  • 0 in reply to Keerthy J
    Prodigy 100 points

    Hi Keerthy!

    Thank you for the response!

    Yes, our requirement is too have ethernet switch functional across Linux(A72) reset and would like how to accomplish that?

    We will use three RGMII MAC/ports in our product and were thinking to use all three from the CPSW9G switch.

    So we wondered which of the two options below we needed to go for.

    We preferred option 1!

    1. Run the Ethernet Driver in the Main R5F and use CPSW9G ethernet switch?
    This needs to be functional across a Linux(A72) reset.

    If I understood you correct this is not possible and during a Linux(A72) reset also the complete Main domain including the R5F cores and CPSW9G will also go through a reset?

    2. Use two RGMII MAC from CPSW9G/Main R5F and the third one from the CPSW2G/MCU R5F in the MCU Domain.
    Across Linux(A72) reset the IP link can be functional through the CPSW2G/MCU R5F but the two RGMII in the main domain will go through a reset.

    Is option 2 the only way forward?

    Thanks!

    Best regards

    Goran

  • 0 in reply to Keerthy J
    Prodigy 73 points
    Keerthy J said:

    The present SDK implementation both U-Boot & Linux reset/reboot use the: https://software-dl.ti.com/tisci/esd/latest/2_tisci_msgs/pm/sysreset.html?highlight=tisci_msg_sys_reset

    Since the boot core is MCU_R5F the entire SoC aka main domain as well as the MCU domain is reset to start afresh.

    When you refere to "the present SDK" I assume this is a situation caused by software and not by hardware limitations? Right? I.e it sound like it should be possible to meet Goran's request by modifications in the SDK?

    Keerthy J said:
    No. The current implementation resets the entire main domain which includes the ethernet switch.

    In section "5.3.6.3 MCU_RESETz sequence" one can read that "another group of modules is partially reset" and then MCU_CPSW0 and CPSW0 is mentioned. What does that mean exactly? 

    In an older SDK version "reset isolation" was mentioned in the context of CPSW: https://software-dl.ti.com/jacinto7/esd/processor-sdk-rtos-jacinto7/07_00_00_11/exports/docs/pdk_jacinto_07_00_00/docs/apiguide/j721e/html/structCpswAle__RestartConfig.html . It seems that is used to be possible to perform a reset without resetting the CPSW? Are there any shortcomings in the hardware that motivated the removal of this feature in the SDK?