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TMS320VC5507: CLKOUT frequency fluctuates

Liu Yang
Expert 5915 points
Part Number: TMS320VC5507
Other Parts Discussed in Thread: TMDSEMU200-U

Hi Team,

DSP register setting:
 * System Register (SYSR) 0x0006
 * Clock Mode Register (CLKMD)  0x6610
 * External Bus Selection Register (EBSR) 0x1203

Peripheral Hardware:
 * Device supply voltageCVDD = 1.6 V (200 MHz)
 * Power supply IC in use TPS79516DCQR

 * X2/CLKIN(13pin) oscillator in use KC2520Z16.3840C15XXK
 * X1(14pin):Open
 * Internal CPU clock:16.384MHz*12=196.608MHz
 * CLKOUT frequency(15pin) :16.384MHz

Problem:
 * The CLKOUT frequency fluctuates by about 0.3MHz.
    (Varies from 60ns to 62ns at 61ns per cycle.)

Conditions:
 * SYSR, CLKMD, EBSR are not rewritten after initial setting.
 * There is no distortion, noise or frequency variation at the oscillator input (pin 13) even when the CLKOUT frequency fluctuates.
 * When software processing is light, CLKOUT frequency fluctuation does not occur.
 * When the software processing is heavy, such as when the multiplier is used frequently, the CLKOUT frequency will fluctuate.
 * It doesn't occur when I run it under the debugger(TMDSEMU200-U).
 * It does not occur when the CPU clock is set to 96MHz.

Question:
 (1) What causes the CLKOUT frequency to fluctuate?
　　 How can I improve?
 (2) Is it okay to drop the CPU clock to 96MHz while keeping CVDD at 1.6V? (although 1.2V is recommended)
 (3) Are you saying that the frequency variation in question is within this range?
       [SPRS244J: Table 5−3. CLKOUT Switching Characteristics (CVDD=1.6V)
           C8 tw(COL) Pulse duration, CLKOUT Low: H + 1, H − 1ns
           C9 tw(COH) Pulse duration, CLKOUT High: H + 1, H − 1ns

Best Regards,
Tom

  • 0
    TI__Intellectual 2665 points

    Hi Tom,

    I would like to understand your implementation better.

    Are you using the clock generation mode in section 5.6.3 in Datasheet?

    What is the BYPASS_DIV setting? Can you share the register settings for getting the CPU clock of 196.608MHz?

    Are you measuring the CLKOUT after nRESET goes high per the Figure 5-15 in Datasheet?

    Thank you,

    Anita

  • 0 in reply to Anita Pratti
    TI__Expert 5915 points

    Hi Anita,

    Q1. Are you using the clock generation mode in section 5.6.3 in Datasheet?

        Ans. Bypass Mode in 5.6.3 is not used because PLLENABLE is set to "1".

     

    Q2. What is the BYPASS_DIV setting?

         Ans. The BYPASS_DIV setting is 00.

                 (The CLKMD register setting is 6610hex.

                 Bits 3 and 2 in the CLKMD register are 00.)

     

    Q3. Can you share the register settings for getting the CPU clock of 196.608MHz?

         Ans. It is set by the CLKMD register.

                 CLKMD register : 6610hex

    　    bit           Field            Value

            15           Reserved      :0

            14           IAI                 :1

            13           IOB                :1

            12           TEST             :0

            11,10,9,8,7  PLLMULT   :01100

             6,5         PLLDIV           :00

             4           PLLENABLE    :1

    　       3,2         BYPASSDIV   :00

             1           BREAKIN         :0

             0           LOCK               :0

     

    Q4. Are you measuring the CLKOUT after nRESET goes high per the Figure 5-15 in Datasheet?

         Ans. I am observing CLKOUT after nRESET.

                Waveform observation in steady state.

                Observed with an oscilloscope using a FET probe.

    ---------------------------------------------------------------------------------------

    In addition, we found the following while conducting a new defect analysis.

     

    Phenomenon:

    I set the AGPIO Direction as follows:

    　　AGPIO_REG.AGPIOEN.all = 0x3fff;

    　　AGPIO_REG.AGPIODIR.all = 0xf00f;

    I coded the following with the intention of writing bit data only to bit12 in the program.

    　　AGPIO_REG.AGPIODATA.bit.AIOD12 = Latch.Sel[0];

    　　　Latch.sel[0] is a word register.

    I found that the above code writes to AGPIO_REG.AGPIODATA.bit.AIOD12 in words. I was writing to an input port.

     

    If the above operation is performed during heavy processing using a multiplier, fluctuations in CLKOUT will occur. If software processing is light, CLKOUT frequency variation will not occur.

    Also, if the above port access is deleted, CLKOUT will not fluctuate even if the processing is heavy.

     

    Question:

    (1) Does CLKOUT fluctuate when writing to the port set for input?

    (2) What can be the cause of the above phenomenon?

    Best Regards,
    Tom

  • 0 in reply to Liu Yang
    TI__Intellectual 2665 points

    Hi Tom,

    This is a device that has no design support beyond the collateral and information available on ti.com as per the note on the product page. Please refer to the product guidance here.

    https://e2e.ti.com/support/processors-group/processors/f/processors-forum/818771/faq-support-guidance-for-c5000-digital-signal-processors

    To answer your questions to the best of the available information

    1) I do not expect the clock to fluctuate due to writing to an input port. 

    2) I could not find anything from the device documents that explains the behavior. But from the your comment on the fluctuation with a certain debugger. It might be related to some noise being coupled in certain conditions. 

     * It doesn't occur when I run it under the debugger(TMDSEMU200-U).

    Thank you,

    Anita