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TDA3MV: Add 1 clock delay in H/V sync in TDA3

Sung-IL
Mastermind 29710 points
Part Number: TDA3MV
Other Parts Discussed in Thread: ADC3542

Dear Champs,

My customer is developing thermal camera using TDA3 and trying to connect IR detector to VIP port of TDA3.

As the output of their IR detector is analog output, they need to attach ADC and need to control it.

Could you please provide how ADC can be attached to TDA3 without any additional MCU?

We are promoting ADC3542, but it has 1 clock delay between input and output and customer is wondering how they can sync-up it with Vsync/Hsync signal.

Is it possible to add 1 clock delay in Hsync and Vsync in TDA3?

Thanks and Best Regards,

SI.

  • 0
    TI__Guru**** 430475 points

    Hi SI,

    Do you mean on the VIP ie input side? No TDA3 cannot add 1 clock cycle delay between hsync and vsync. VIP is input port, so it is receiving hs and vs signals.. May be you could change clock edge and thus can delay detection by half clock cycle. VIP does not delay them.. 

    When is exactly this delay coming frame? Is it also affecting data from the ADC output? Typically VIP will capture during VS and HS active low period, so this is taken care, VIP would be able to capture the data.. 

     

    Regards,

    Brijesh

  • 0 in reply to Brijesh Jadav
    TI__Mastermind 29710 points

    Hi Brijesh,

    Thanks for immediate response, and I'm sorry for my wrong description.

    Let me explain their system configuration as below.

    IR detector output analog data, clock, H/V sync and these H/V sync will connected to TDA3 VIP port directly and analog data and clock will be connected to TDA3 VIP port through ADC with 1 clock delay as below.

    e.g. there will be 1 clock delay in real pixel at initial and I would like to check if we can adjust it in SW to capture pixel data correctly.

    Thanks and Best Regards,

    SI.

  • +1 in reply to Sung-IL
    TI__Guru**** 430475 points

    Hi SI,

    Unfortunately, this cannot be done in the SW. In this case, i would suggest to put additional delay circuit on HS and VS lines to delay them by a clock cycle and keep it in sync with data output from ADC. 

    Regards,

    Brijesh