DRA821U: ADC Underflow Interrupt Trigger

In a normal use case, this underflow should never occur. The typical case is to use ADC_FIFO0WC and ADC_FIFO1WC to determine how many words are in the FIFO.

Kevin

Hi Kevin.

Thank you for your response.

we found a procedure to generate a FIFO underflow interrupt in the PDK sample application.

The procedure is as follows.
(1) Load csl_adc_singleshot_test_app (adc_app.c).
(2) Set a breakpoint at line 474 of adc_app.c.
(3) Resume csl_adc_singleshot_test_app.
(4) Wait for 1 second after the break at line 474 of adc_app.c.
(5) Step over from line 474 of adc_app.c.
(6) As shown in the attached screen capture, FIFO0 and FIFO1 underflow interrupts occur.

What is the cause of the FIFO0 and FIF01 underflow interrupts in the above procedure?
In particular, csl_adc_singleshot_test_app does not use FIFO1.

We assume that the FIFO underflow occurs when the ADC module remains enabled after the end of single conversion (one-shot mode).

Regards.

Hi Kevin.

We attach a screen capture.

Tomitama,

The underflow is a statement that you tried to read the FIFO when there was nothing to read. In a normal operation, you should not run into this because ADC_FIFO0WC and ADC_FIFO1WC indicate how many entries remain in the FIFO.

Kevin

Hi Kevin.

Thank you for your response.

In the procedure using csl_adc_singleshot_test_app, the following FIFO underflow interrupt occurred.

Line 474 of adc_app.c generated a FIFO0 underflow interrupt even though it was after reading ADC_FIFO0WC and ADC_FIFO0DATA.
The FIFO1 underflow interrupt occurred even though csl_adc_singleshot_test_app has never read ADC_FIFO1WC and ADC_FIFO1DATA.

In other words, we want to know what causes the FIFO underflow interrupt in line 474 of adc_app.c where FIFO0 and FIFO1 are not read.

Regards.

Tomitama-san, this new question is a SW related question so moving ownership from Kevin to SW team.  They will review new questions and respond.

Hi,

tomitama said:

Line 474 of adc_app.c generated a FIFO0 underflow interrupt even though it was after reading ADC_FIFO0WC and ADC_FIFO0DATA.
The FIFO1 underflow interrupt occurred even though csl_adc_singleshot_test_app has never read ADC_FIFO1WC and ADC_FIFO1DATA.

Can you please confirm what values are you reading for ADC_FIFO0WC  and ADC_FIFO1WC before you run Line 474?

Regards,
Parth

Hi Parth.

Thank you for your response.

The values of ADC_FIFO0WC and ADC_FIFO1WC were as follows.
After the FIFO underflow interrupt occurs, the values of ADC_FIFO0WC and ADC_FIFO1WC seem to be decremented.

(1) Line 299 (just before getting data from FIFO0)
ADC_FIFO0WC:5
ADC_FIF10WC:0

(2) Line 461 (just after getting data from FIFO0)
ADC_FIFO0WC:0
ADC_FIF10WC:0

(3)Line 474 (before FIFO underflow interrupt occurs)
ADC_FIFO0WC:0
ADC_FIFO0WC:0

(4) Line 474 (after FIFO underflow interrupt occurs)
ADC_FIFO0WC:511
ADC_FIF10WC:506

(5) Line 474 (after FIFO underflow interrupt occurs)
ADC_FIFO0WC:510
ADC_FIF10WC:505

Regards.

Additional information.

After removing the FIFO read from the CCS register window(*), the FIFO underflow interrupt no longer occurs in csl_adc_singleshot_test_app.
When the ADC module is enabled and the FIFO is empty, does reading the FIFO from the debugger cause a FIFO underflow interrupt?

(*)Removed register id tags for ADC_FIFO0DATA and ADC_FIFO1DATA from "MCU_ADC0.xml" in CCS.

Hi Tomitama-san,

tomitama said:

When the ADC module is enabled and the FIFO is empty, does reading the FIFO from the debugger cause a FIFO underflow interrupt?

Yes, this is entirely possible. Reading from the debugger is just an another way of reading the data form software. And if software tries to read the FIFO when it is empty, underflow interrupt will be triggered

Regards,
Parth