How to calculate the "DDR3 Interface – Registers" for Keystone I devices and Test/Debug on Keystone I EVM ?
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How to calculate the "DDR3 Interface – Registers" for Keystone I devices - ( C6657 / C6678 ) and Test/Debug on Keystone I EVM ?
The FAQ already exists for Keystone II devices. The procedure is same. Please use the documents and gel files of Keystone I devices instead of Keystone - II.
Documents to read at first sight:
1. Design requirements - https://www.ti.com/lit/an/sprabi1d/sprabi1d.pdf
2.Keyston I Interface bring - up - https://www.ti.com/lit/an/spracl8/spracl8.pdf
3. KeyStone I DDR3 Initialization - https://www.ti.com/lit/an/sprabl2e/sprabl2e.pdf
4. Keystone Architecture DDR3 Memory Controller - https://www.ti.com/lit/ug/sprugv8e/sprugv8e.pdf
The rest, follow the instructions given in the FAQ of Keystone II. :-[FAQ] 66AK2E05: How to calculate the "DDR3 Interface – Registers" for Keystone II devices and Test/Debug on Keystone II EVM. - Processors forum - Processors - TI E2E support forums
In-place of spread sheet and DDR3 guide of Keystone II, have the spread sheet and guide-notes of Keystone I.
There is no debug gel file available for Keystone -I devices.