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AM6442: AM64x RMII IOSet

Part Number: AM6442

Hello,

In our design we need to use IOSet1 for all RMII signals but RMII_REF_CLK needs to be on IOSet2 (AA5). What is the expected additional delay of RMII_REF_CLK on AA5 in ns compared to signals in IOSet1?

Thank you.

  • Hello MH, 

    Thank you for the query.

    Can you share the picture of the configuration you have tried.

    Have you looked at the TRM for the allowed RMII configuration.

    Regards,

    Sreenivasa

  • Hello Sreenivasa,

    The configuration is below and is shown vs TRM:

    This config is functional but I need to know what are the margins, again this is 100BaseTX so 50MHz clk, not RGMII (250MHz signals). So the question to you is:

    1- Does the signal RMII_REF_CLK on IOSet2 (PRG0_PRU0_GPO10) has a shorter propagation delay within the chip or longer versus the group delay of IOSet1.

    2- by how much?

    Thank you.

  • Hello MH, 

    Thank you for the inputs.

    Let me check internally and update you.

    Please expect some delay as i reach out to the experts.

    Regards,

    Sreenivasa

  • Hello MH, 

    Please read note 1 below the table 

    (1) RMII_REF_CLK is common to both RMII1 and RMII2. For proper operation, all pin multiplexed
    signal assignments must use the same IOSET.

    The device does not support the above configuration.

    Both RMII ports share a single RMII_REF_CLK.  This clock can be sourced to the PRG1_PRU0_GPO10 pin (U14) for IOSET1 or the  PRG1_PRU0_GPO10 pin (AA5) for IOSET2.  All RMII signals must be configured to pins associated with IOSET1 or IOSET2.  It is not possible to split the assignment between IOSETs.  The clock path for each IOSET is timing closed relative to the signals associated with its respective IOSET.  So the delay difference between the two clock paths is not relative.

    Regards,

    Sreenivasa

  • Hello,

    My question was not about the support of mixed IOSets support (which is clear in the TRM and in your response) but rather the expected difference in propagation delays from pin U14 (with MUX set to RMII_REF_CLK) to the MAC peripheral and from pin AA5 (with MUX set to RMII_REF_CLK) to the MAC module.

    Thank you

  • Hello MH,

    Thank you for the reply.

    I extracted the below from the previous reply.

    The clock path for each IOSET is timing closed relative to the signals associated with its respective IOSET. 

    but rather the expected difference in propagation delays from pin U14 (with MUX set to RMII_REF_CLK) to the MAC peripheral and from pin AA5 (with MUX set to RMII_REF_CLK) to the MAC module

    This is not a use case that is supported.

    Regards,

    Sreenivasa