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AM6442: AM64x SEVI documentation

Part Number: AM6442

For performance tuning I’m interested in getting the interrupts working for the PKTDMA.  In the TRM 11.1.4.3 PTKDMA/BCDMA – Output Event Generation, it says that, "Events are output from the DMA controllers using a simple integer encoding.” and, “The index field on this ETL will be calculated based on the event type and channel or flow offset. Each PKTDMA or BCDMA instance is configured with base values to which a channel or flow index is added for each type of event which can be generated. These base index values are listed in the specification for that specific instantiation of each DMA…”, but those base index values are not listed anywhere.

 As an experiment I enabled all 1536 SEVI interrupts to see which would trigger and only one did, number 30.  I’m assuming 30 is the PKTDMA RX complete event, based on some observations, but I’d like to know for sure.  I’d also like to know why we’re not seeing any other events trigger, I would expect some TX completion events as well.

 Here is the code we’re using to turn on the interrupts;

hwm_gp_outp64( &INTAGGR_IMAP[ SEVI ], ( VINTR << 8 ) | BITNUM );

hwm_gp_outp64( &INTAGGR_INTR[ VINTR ].STATUS_CLEAR, setbit( BITNUM ) );

hwm_gp_outp64( &INTAGGR_INTR[ VINTR ].ENABLE_SET  , setbit( BITNUM ) );

 

11.2.4.4.1.6 DMASS0_INTAGGR_0_INTMAP

11.2.4.4.1.4 DMASS0_INTAGGR_0_STATUS

11.2.4.4.1.1 DMASS0_INTAGGR_0_ENABLE_SET

  • Brad, 

    It seems like the documentation is not robust with regard to interrupt index mapping. I will file an issue against this so we can track and try and resolve in the next revision. 

    Let me try and fill in gaps here. Below is the global index mapping for the INTAGGR unmapped events:

    You can see that PKTDMA events are routed to unmapped events in the IntAggr which need to be configured in the system. The formula to calculate which unmapped interrupt is TX/RX event base + TX/RX channel number. 

    Unmapped interrupts need to be mapped to a global event output by configuring the intaggr so they can be used in the system. I am pasting a code snipped below that shows an example using CSL code:

        if (CSL_intaggrMapUnmappedEventToEvent(dmss.pIntAggrCfg, tx_event_num, TX_COMPLETION_STATUS|CSL_INTAGGR_INTR_MODE_FLAG ) != 0)
        {
            printf( "CSL_intaggrMapEventIntr() failed\n" );
        }
    
        if(CSL_intaggrSetIntrEnable( dmss.pIntAggrCfg, TX_COMPLETION_STATUS, TRUE ) != 0)
        {
            printf( "CSL_intaggrSetIntrEnable() failed\n" );
        }
        if (CSL_intaggrMapUnmappedEventToEvent(dmss.pIntAggrCfg, rx_event_num, RX_COMPLETION_STATUS|CSL_INTAGGR_INTR_MODE_FLAG ) != 0)
        {
            printf( "CSL_intaggrMapEventIntr() failed\n" );
        }
    
        if(CSL_intaggrSetIntrEnable( dmss.pIntAggrCfg, RX_COMPLETION_STATUS, TRUE ) != 0)
        {
            printf( "CSL_intaggrSetIntrEnable() failed\n" );
        }

    In this case, TX_COMPLETION_STATUS and RX_COMPLETION_STATUS are an arbitrary global index output from the intAggr. 

    Please let me know if any follow up questions are required.

    Thanks,

    Chris 

  • It still doesn't work following the chart and example code.  I've enabled all the events for the CPSW and again only the RX Completion even seems to work.  Below is my code for enabling all the CPSW events.  I got the channel and flow offsets from the PDK 5.9.1.1.3.

    struct intaggr_intr * const INTAGGR_INTR = (void *)0x48000000; // 0 - B7 184
    uint64              * const INTAGGR_UMAP = (void *)0x48180000; // 0 - 3014 12308

    #define TX_CHAN_ERROR_BASE      ( 4096 ) // 42
    #define TX_FLOW_COMPLETION_BASE ( 4608 ) // 112
    #define RX_CHAN_ERROR_BASE      ( 5120 ) // 29
    #define RX_FLOW_COMPLETION_BASE ( 5632 ) // 176
    #define RX_FLOW_STARVATION_BASE ( 6144 ) // 176
    #define RX_FLOW_FIREWALL_BASE   ( 6656 ) // 1

    const int offset[] = {
      TX_CHAN_ERROR_BASE + 16
    , TX_FLOW_COMPLETION_BASE + 16
    , RX_CHAN_ERROR_BASE + 16
    , RX_FLOW_COMPLETION_BASE + 16
    , RX_FLOW_STARVATION_BASE + 16
    , RX_FLOW_FIREWALL_BASE };

    const int length[] = {
      8
    , 64
    , 1
    , 16
    , 16
    , 1 };

    for( int b = 0; b < cnt_of_array( offset ); ++b )
    {
      for( int i = 0; i < length[ b ]; ++i )
      {
        hwm_gp_outp64( &INTAGGR_UMAP[ offset[ b ] + i ], IRQMODE | ( b << 6 ) | i );
        hwm_gp_outp64( &INTAGGR_INTR[ b ].STATUS_CLEAR, setbit( i ) );
        hwm_gp_outp64( &INTAGGR_INTR[ b ].ENABLE_SET , setbit( i ) );
      }
      hwm_intc_register_handler( GICBASE + b, event_handler );
    }

  • Jason,

    I am looping in a software expert to help try and address this.

    Thanks,

    Chris

  • Those links tell me how to generate or use an SCI Client board configuration for use with GPIO interrupts.

    Unfortunately, I am unable to use the SCI Client as my project cannot use the SCI firmware.  I did compare the default board config referenced in the links to the code I provided above and concluded that they essentially have the same offsets and lengths.  And my code is performing the same operations as the SCI Client.

  • Hello ,

    I am currently working on your issue. Please provide your feedback on the following queries so that I can better understand your requirements.

    The AM64X has GPIO interrupt routers, clock settings, Reset  and other security operations that should only be done by the SYSFW.

    Currently, the user cannot directly control the Registers for the above operations. If you attempted, the SOC may enter an exception state. This means that the DMSC core only has permission to write and read from the Register set, while other cores only have read permission.

    Could you please explain how you controlled the GPIO interrupt router and clock settings to the CPU and other operations without using the SCI client in your application?

    Could you briefly explain your requirements?

    Regards,

    S.Anil.

  • I think I've got it working now.  Using the chart and example code and PDK, it did work, I just wasn't tracking multiple events per period and so I was only seeing the last even, the RX Completion.  I've altered my code to track all events before reporting now.

  • Hello ,

    Thanks for your input, and I will share this information with the CPSW expert since I am not fully aware of it.

    Do you need any other support? Please let me know, and I can direct your queries to the CPSW expert.

    Regards,

    S.Anil.