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TDA4VM-Q1: How to get the actual LPDDR4 Vref value of TDA4VM-Q1

Part Number: TDA4VM-Q1
Other Parts Discussed in Thread: TDA4VM

Hello TI experts,

I have a question about LPDDR4 Vref value for TDA4VM SOC.

We can set DDRSS_CTL_180 register to program DDR MR14 register. So DDR Vref can be defined by it. However, the DDR Vref training function is also enabled.  Register  DDRSS_PI_61 is 10020101. Then I'm confused about what is the actual LPDDR4 Vref value.

Questions:

1.How to get the actual LPDDR4 Vref value?

2. Is it always changing when DDR works, or is it only adjusted once during DDR initializes?

  • Hi,

    You are correct that the DRAM CA and DQ VREF values are trained during initialization. 

    1) You can read out the DQ VREF values after initialization from the PI_MR14_DATA_F*_* parameters. See registers PI_278, 280, 284, 286, 290, 292, 296, 298.

    2) The Jacinto7 DDR Register Config Tool configures the DDRSS such that the LP4 DQ VREF values are only adjusted once during DDR initialization and are not re-trained during normal operation. This is true for all existing versions of the tool up to this point in time (current version is v0.10.0).

    Regards,
    Kevin