Other Parts Discussed in Thread: TUSB320
I have built the "hello_world" example for the AM263x successfully. However, when I start the debug session I get the error in the title line. I have tested the JTAG connection and it passes. I have also experimented with different TCLK frequencies (down to 1.25 MHz) to no avail.
Here is the console messages:
Cortex_R5_0: GEL Output: Loading Gel Files on R5F0
Cortex_R5_0: GEL Output: Gel files loading on R5F0 Complete
Cortex_R5_0: GEL Output: ***OnTargetConnect() Launched***
Cortex_R5_0: GEL Output: AM263x Initialization Scripts Launched.
Please Wait...
Cortex_R5_0: GEL Output: AM263x_Cryst_Clock_Loss_Status() Launched
Cortex_R5_0: GEL Output: Crystal Clock present
Cortex_R5_0: GEL Output: AM263x_SOP_Mode() Launched
Cortex_R5_0: GEL Output: SOP MODE = 0x00000000
Cortex_R5_0: GEL Output:
QSPI - 4S Functional boot mode
Cortex_R5_0: GEL Output: AM263x_Read_Device_Type() Launched
Cortex_R5_0: GEL Output: EFuse Device Type Value = 0x000000AA
Cortex_R5_0: GEL Output: AM263x_Check_supported_mode() Launched
Cortex_R5_0: GEL Output:
efuse1=0x01000000
Cortex_R5_0: GEL Output:
The Device supports both LockStep & Dual Core mode
Cortex_R5_0: GEL Output:
mode = 0
Cortex_R5_0: GEL Output: MSS_CTRL Control Registers Unlocked
Cortex_R5_0: GEL Output: MSS_TOP_RCM Control Registers Unlocked
Cortex_R5_0: GEL Output: MSS_RCM Control Registers Unlocked
Cortex_R5_0: GEL Output: MSS_IOMUX Control Registers Unlocked
Cortex_R5_0: GEL Output: TOP_CTRL Control Registers Unlocked
Cortex_R5_0: GEL Output:
***R5FSS0 Reset for Lockstep ***
Cortex_R5_0: GEL Output:
*** R5FSS1 Reset for Lockstep ***
Cortex_R5_0: GEL Output: R5F ROM Eclipse
Cortex_R5_0: GEL Output: R5FSS0_0 Released
Cortex_R5_0: GEL Output: R5FSS0_1 Released
Cortex_R5_0: GEL Output: R5FSS1_0 Released
Cortex_R5_0: GEL Output: R5FSS1_1 Released
Cortex_R5_0: GEL Output:
All R5F Cores Released for program load
Cortex_R5_0: GEL Output: L2 Mem Init Complete
Cortex_R5_0: GEL Output: MailBox Mem Init Complete
Cortex_R5_0: GEL Output: *********** R5FSS0/1 Lockstep mode Configured********
Cortex_R5_0: GEL Output: SYS_CLK DIVBY2
Cortex_R5_0: GEL Output: DPLL_CORE_HSDIV0_CLKOUT0 selected as CLK source for R5FSS & SYS CLKs
Cortex_R5_0: GEL Output:
CLK Programmed R5F=400MHz and SYS_CLK=200MHz
Cortex_R5_0: GEL Output:
*** Enabling Peripheral Clocks ***
Cortex_R5_0: GEL Output: Enabling RTI[0:3] Clocks
Cortex_R5_0: GEL Output: Enabling RTI_WDT[0:3] Clocks
Cortex_R5_0: GEL Output: Enabling UART[0:5]/LIN[0:5] Clocks
Cortex_R5_0: GEL Output: Enabling QSPI Clocks
Cortex_R5_0: GEL Output: Enabling I2C Clocks
Cortex_R5_0: GEL Output: Enabling TRACE Clocks
Cortex_R5_0: GEL Output: Enabling MCAN[0:3] Clocks
Cortex_R5_0: GEL Output: Enabling GPMC Clocks
Cortex_R5_0: GEL Output: Enabling ELM Clocks
Cortex_R5_0: GEL Output: Enabling MMCSD Clocks
Cortex_R5_0: GEL Output: Enabling MCSPI[0:4] Clocks
Cortex_R5_0: GEL Output: Enabling CONTROLSS Clocks
Cortex_R5_0: GEL Output: Enabling CPTS Clocks
Cortex_R5_0: GEL Output: Enabling RGMI[5,50,250] Clocks
Cortex_R5_0: GEL Output: Enabling XTAL_TEMPSENSE_32K Clocks
Cortex_R5_0: GEL Output: Enabling XTAL_MMC_32K Clocks
Cortex_R5_0: GEL Output:
***All IP Clocks are Enabled***
Cortex_R5_0: GEL Output: CPU reset (soft reset) has been issued through GEL.
Cortex_M4_0: Error connecting to the target: (Error -1170 @ 0x0) Unable to access the DAP. Reset the device, and retry the operation. If error persists, confirm configuration, power-cycle the board, and/or try more reliable JTAG settings (e.g. lower TCLK). (Emulation package 9.10.0.00080)
