Other Parts Discussed in Thread: OMAPL138
I'm working on omapl138 custom board in that I'm facing throughput issue between emifa processor to FPGA. There's no data integrity issue between the both. Currently I'm using asynchronous mode of emif for that I'm using chip select 2. If I go with asynchronous mode there's gap of between every data 100khz it's too slow i can't achieve my throughput.
I don't find any SDRam(configuration) of chip select 0 because it's synchronised with emifa_clock. I want synchronised with clock of emifa configuration.
Please if anyone knows kindly share it with me.
Thanks & Regards