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Other Parts Discussed in Thread: OMAPL138

Hello all,

I'm working on omapl138 custom board in that I'm facing throughput issue between emifa processor to FPGA. There's no data integrity issue between the both. Currently I'm using asynchronous mode of emif for that I'm using chip select 2. If I go with asynchronous mode there's gap of between every data 100khz it's too slow i can't achieve my throughput. 

I don't find any SDRam(configuration) of chip select 0 because it's synchronised with emifa_clock. I want synchronised with clock of emifa configuration.

Please if anyone knows kindly share it with me.

Thanks & Regards


  • Please check the timing parameters that are described in section 20.2.5 of the TRM.   Can you dump those registers and check to make sure you have optimized timings based on your FPGA timings.  Do you have a scope shot of the problem transactions?  You might also want to check the MMU settings (if they are enabled) of the processor you are using to perform the transactions.  These may be restricting the accesses (for example, you might have this region setup as strongly ordered)