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Original question:

DRA821U: SERDES REFCLOCK (PCIe) Reference Clock Input Characteristics

DRA821U: PCIe termination resistors and SI

Syed N Akhtar
Prodigy 120 points

Part Number: DRA821U
Other Parts Discussed in Thread: DRA821

This questions is related to the following thread:

https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1082419/dra821u-serdes-refclock-pcie-reference-clock-input-characteristics

How do I disable termination resistors for PCIe in DRA821? Is it required to disable PCIe termination resistors before Refclk comes up for all HCSL CLk driver output (PI6C557-03B or PI6CG18801)?

What SI optimization options does DRA have for PCIe (e.g.)  pre emphasis and equalization settings?

Does TI have recommended SI settings base on board parameters ( use X pre emphasis for trace length Y)?

  • 0
    Prodigy 90 points

    For the termination, I found that there is bit 27 in the SERDES_RST register (0506040c) that talks about disabling termination. This appears to be how to disable the termination resistor, but confirmation from the TI side would be helpful. 

  • 0 in reply to James Windorff
    TI__Genius 17156 points

    Yes, DRA821 supports PCIe-standard link autonomous equalization upon training to 8.0GT/s speed. This is an automatic negotiation between link partners to adjust the Transmitter and the Receiver setup of each Lane to improve the signal quality. Software can optionally set Preset Hints per the PCIe standard if desired, based on their system requirements.