Hello,
I'm trying to port a c66 DSP firmware initially developed as baremetal application (without TI-RTOS) and not compatible with a running Linux OS on the ARM core.
This firmware is based on a TI demo where all the board support is initialized (pinmux, DDR etc).
Also the IPC stack and the remoteproc support was not supported since TI-RTOS is mandatory dependecy required by the TI IPC 3.x stack.
This initial firmware contains some time critical (low latency) code I need to take care.
Since the TI-RTOS and the IPC 3.x stack is required, I started from the "big-data-ipc-examples" project.
For now I don't need the CMEM API support to share more memory between the ARM and the DSP, so I removed all the CMEM initialization and now the code
base look like more to MessageQApp.c example from the ipcdev test program but with a customized ressource_table.
I noticed that the linker file generated by the "big-data-ipc-examples" build system is really different from the handwritten linker file from the baremetal project.
Indeed most of the baremetal firmware section where located on the DSP L2SRAM but the "big-data-ipc-examples" uses the DDR instead.
The L2SRAM is prefered due to timing constraints.
Here the extract of the baremetal linker (.cmd) script:
SECTIONS
{
BOARD_IO_DELAY_DATA : load > L2SRAM
BOARD_IO_DELAY_CODE : load > L2SRAM
.csl_vect : > RST_START
GROUP: load > L2SRAM
{
.bss:
.neardata:
.rodata:
}
.vects > L2SRAM
.l2_int > L2SRAM
.pmIdleFunc > L2SRAM
.text:_c_int00 > L2SRAM
.text:_isr > L2SRAM
.text > L2SRAM
.bss > L2SRAM
.data > L2SRAM
.sysmem > L2SRAM
.stack > L2SRAM
.cinit > L2SRAM
.const > L2SRAM
.cio > L2SRAM
.testData > L2SRAM
.init_array > L2SRAM
.init > L2SRAM
.far > L2SRAM
.plt > L2SRAM
.fardata > L2SRAM
.switch > L2SRAM
}
Now the generated linker.cmd look like:
MEMORY
{
L2SRAM (RWX) : org = 0x800000, len = 0x48000
OCMC_RAM1 (RWX) : org = 0x40300000, len = 0x80000
OCMC_RAM2 (RWX) : org = 0x40400000, len = 0x100000
OCMC_RAM3 (RWX) : org = 0x40500000, len = 0x100000
EXT_CODE (RWX) : org = 0x95000000, len = 0x100000
EXT_DATA (RW) : org = 0x95100000, len = 0x100000
EXT_HEAP (RW) : org = 0x95200000, len = 0x300000
TRACE_BUF (RW) : org = 0x9f000000, len = 0x60000
EXC_DATA (RW) : org = 0x9f060000, len = 0x10000
PM_DATA (RWX) : org = 0x9f070000, len = 0x20000
}
SECTIONS
{
.text: load >> EXT_CODE
.ti.decompress: load > EXT_CODE
.stack: load > EXT_DATA
GROUP: load > EXT_DATA
{
.bss:
.neardata:
.rodata:
}
.cinit: load > EXT_DATA
.pinit: load >> EXT_DATA
.init_array: load > EXT_DATA
.const: load >> EXT_DATA
.data: load >> EXT_DATA
.fardata: load >> EXT_DATA
.switch: load >> EXT_DATA
.sysmem: load > EXT_DATA
.far: load >> EXT_DATA
.args: load > EXT_DATA align = 0x4, fill = 0 {_argsize = 0x64; }
.cio: load >> EXT_DATA
.ti.handler_table: load > EXT_DATA
.c6xabi.exidx: load > EXT_DATA
.c6xabi.extab: load >> EXT_DATA
.tracebuf: load > EXT_DATA
.resource_table: load > 0x40800000, type = NOINIT
.vecs: load > EXT_CODE
xdc.meta: load > EXT_DATA, type = COPY
}
Indeed EXT_CODE, EXT_DATA and EXT_HEAP refers to the DDR memory.
Do you think it is doable to use the L2SRAM instead of the DDR ?
We also want to keep the IPC stack working with Linux.
AFIAK, I need to customize (or remove?) the externalMemoryMap from config.bld
and customize the ressource_table to use L2SRAM address for DSP_MEM_TEXT,
DSP_MEM_DATA, DSP_MEM_HEAP0, DSP_MEM_HEAP1.
Is the remoteproc driver able to load an DSP firmware using sections to L2SRAM?
[1] https://git.ti.com/cgit/processor-sdk/big-data-ipc-examples/tree/host_linux/simple_buffer_example/shared/DRA7XX/config.bld?h=01.03.00.00#n51
Best regards,
Romain