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TDA4VM-Q1: Two TDA4VH chips connect the MAC to MAC through the RGMII interface of the main domain; Gigabit communication debugging failed

夏琨 陈
Prodigy 20 points
Part Number: TDA4VM-Q1
Other Parts Discussed in Thread: TDA4VH

Two TDA4VH chips connect the MAC to MAC through the RGMII interface of the main domain; Gigabit communication debugging failed; The oscilloscope measurement shows that the TX data signal cannot be reached chip's level threshold; As shown in the figure below, data 01 is followed by 11, resulting in the level of 0 being raised. Similarly, 10 is followed by 00, resulting in 1 level being pulled down. I feel that the data-driven ability is too poor; Could you help me  if there are registers that can be configured and modified to improve the driving ability of data signals? In addition, why is the clock signal normal for the same length?

  • 0
    TI__Guru 59350 points

    Chen,

    The clk and data have the same drive strength. However, the clk is always toggling. It may not reach the full scale voltages (Vcc/Gnd) when constantly toggling.while the TX because of the repeated bits (00 or 11) it will have enough time to go down to the Gnd or Vcc level. and then when there is another bit transition, it will not have enough time to reach to the rails (Vcc or gnd).

    It seems that IBIS simulation may be worth pursuing based on the PCB trace lengths of the TX / RX / CLK channel. The trace lengths may be long enough / lossy enough that they may not support the required rise/ fall times.

    Please refer to the FAQ to see the drive strength control for RGMII.

    e2e.ti.com/.../faq-tda4vm-q1-tda4-drive-strength-controls

  • 0 in reply to ShreyasRao
    Prodigy 20 points

    Thank you for answering my question；I have tried to modify the register to improve the driving ability of the data signal, but it didn't work. The PCB trace lengths of the TX / RX / CLK channel are about 8000 mil,Whether it meets the requirements of the TDA4VH chip RGMII interface design requirement？

  • 0 in reply to 夏琨 陈
    TI__Guru 59350 points

    Would there be an improvement if you reduced the speed to 10/100M mode? Having these simulations using the IBIS modeling would tell if it meets the RGMII timing requirements. It would also be good to compare the actual vs the modeled values.

  • 0 in reply to ShreyasRao
    Prodigy 20 points

    The speed to 100M mode is OK .IBIS modeling and simulation is in progress.The attached document is the PCB drawing of the RGMII signal part，Can you help check if there is any problem with the PCB design?

    PCB.brd

  • 0 in reply to 夏琨 陈
    TI__Mastermind 47140 points

    What are the in-line resistors near both devices?  Series termination should not be required as IO output impedances are set to match 50-ohms.  Are board impedances controlled/set to 50-ohms?

    Another recommendation would be to route TX signals on same layers - this helps match the skew across the interface.  Different number of vias and routing on different layers can cause signal propagation delays to be different.  (Similar comments for RX signals).

    For the scope captures, where are the probes located?  Please use high speed prove with very short GND connection for accurate images.

    As mentioned, the trace lengths may be long enough / lossy enough that they may not support the required rise/ fall times. 

  • 0 in reply to Robert Eschler
    Prodigy 20 points

    The series resistance is 0 ohms, and the PCB wiring impedance is about 45 ohms.

    Now there is a question. Through the IBIS simulation model and extracting the S parameters of the PCB board for simulation analysis, the simulation results are not very poor and can meet the high and low threshold of the signal.But the signal measured by high-speed oscilloscope is really poor (The test position of the probe is at the via of the chip at the receiving end, and the GND is very short); At present, it seems that the IBIS simulation model is inconsistent with the actual test.

    Disconnect the load and measure the TXCLK signal at the chip sending source. It is found that the slope of the rising edge of the clock waveform is very slow; Is this the lack of drive capability of the chip itself?

  • 0 in reply to 夏琨 陈
    TI__Mastermind 47140 points

    What does the above picture look like if captured at the 'removed load'?  With a 8000mil trace and measuring at the source, the above scope capture likely has transmission like effects.  

  • 0 in reply to Robert Eschler
    Prodigy 20 points
      • The above image measurement position is at the source disconnection string resistance,the trace of the 8000mil PCB has been disconnected,the measurement point is about 400 mil away from the chip.
      • In our experience,RGMII pin locate at MCASP BANK.Too many multiple functions may produce more capacitive reactance.Is the problem caused by the backflow current between the multiplexed pins?
      • Is there any other method to improve drive capability.
  • 0 in reply to jia hao
    TI__Mastermind 47140 points

    To confirm your configuration - the scope image provided is disconnected from the load/long trace. Connected is approx 400mil of trace and a measurement point.  Is that correct?

    Regarding the drive capability - that information was provided previously in this E2E.

    What is the power supply voltage for the VDDSHV power rail?  is it low, causing the IO max voltage to be reduced?  Or does it dip during RGMII usage due to high inductance/insufficient decoupling on the IO power rail?