Other Parts Discussed in Thread: DRA829
*This is a repos*
Hello experts,
Please allow me to check if the following waveforms are acceptable for the power down sequence of the DRA829 when the PMIC is not used.
Currently, on a board designed by the customer, the power down sequence of the DRA829 does not follow described in "7.10.2.5 Isolated MCU and Main Domains, Primary Power- Down Sequencing" of the datasheet. PMIC is not used and power is generated by DCDC or LDO.
Q1:May I assume that the following waveforms are within the acceptable range?
Q2:In particular, VDD_PHYIO_1V8 used in VDDA_1P8_*** is lagging behind other power supplies, is there any possibility of damaging the DRA829?
Attached below are the OFF sequence waveforms, datasheet recommendations, and the power supply circuit for the DRA829.
It would be helpful if you could let us know what concerns you have if the recommendation is violated as in this waveform.
If you have difficulty in responding, we would appreciate it if you could contact us via private chat.
Best regards,
O.H
