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TDA2P-ACD: ECU output video with MAX9295A to MAX9296A. I configure the time parameter of DSS following the formula, but get a green screen on the MAX9296A side.

Part Number: TDA2P-ACD


I'm a software engineer in Valeo. Now I want to output a video stream through MAX9295A to MAX9296A.

The resolution is 1704 * 1080.  Stream type is YUV422(YUYV). Fps is 30.

On ECU, the TDA2P chip is connected to MAX9295A through a parallel link that uses 8 signal lines. MAX9295A is connected to MAX9296A through a coax link.

I configured the time parameters as follow:

    HFP = 9, HBP = 9, HSW = 153

    VFP = 4, VBP = 4, VSW = 32

    FPS = 30

    PCLK = 126000000

    according to the formula:

        PCLK = (HFP + HBP + HSW + 1704 ) * 2 * (VFP + VBP + VSW + 1080) * 30

Then I get a green screen on the MAX9296A side which connected to a Dothinkey box. It seems like a green cloth covering on the screen. No video stream behind the green cloth.

But if I configure the time parameters that do not conform to the formula, the Dothinkey box displays well. The parameters are as follow:

    HFP = 2, HBP = 2, HSW = 116

    VFP = 1, VBP = 1, VSW = 28

    FPS = 30

    PCLK = 126000000

My question is : Why it doesn't work well when conforming to the formula? Is the frequency of PCLK not supported?

Thank you very much!

  • Hi,

    What i am suspecting is,

    - you are sending 2 bytes of pixel over two clock cycles, ie enabling TDM mode in DSS

    - this means hsw will be multiplied by 2 in the driver.

    - But the max hsw supported is 256. 

    - with 153 hsw, it will be go beyond the supported limit

    - but with 116 hsw, it will be still be within supported hsw limit. 

    So it is not an issue with pixel clock, but incorrect hsw. if you select hsw, such that it is within 256 clock cycle limit, it should work. 



  • Thank Brijesh Jadav.  I configure HFP=27, HBP=27, HSW=117, VFP=6, VBP=6, FPS=30, PCLK=126000000. It works now.