Hi TI Experts,
Can you provide a List of collaterals that can be referred when starting a custom board hardware design.
Hi Board designers,
The below links are a quick reference to the collaterals that can be referred when starting a custom design.
Device Selection and features
Product Page
https://www.ti.com/product/AM62A7
https://www.ti.com/product/AM62A7-Q1
Datasheet
AM62Ax Sitara
Processors datasheet (ti.com)
Silicon Errata
AM62Ax Sitara Processors Silicon Errata, Silicon Revision 1.0 (ti.com)
Technical Reference Manual (TRM)
AM62Ax Sitara Processors Technical Reference Manual (ti.com)
Custom Board design
Hardware Design Guide
Hardware Design Guide for AM62A Devices (ti.com)
Schematic Design and Review Checklist
AM62x Schematic Review Checklist (Rev. A)
Power Consumption
AM62Ax Maximum Current Ratings
AM62Ax Power-Estimation Tool (PET)
Evaluation - EVM
SK-AM62A-LP Evaluation board | TI.com
Board Dimensions 2D
7028.PROC135E2_BRD_Dimension.pdf
Board Stackup
3D CAD
PinMux
Schematics (Reference) for RMII interface
Note: We did functionally validate the common clock configuration. No other clocking options were tested.
CAD symbols
Cad symbol specific to the selected device can be chosen from the device product page. Refer below example.
https://www.ti.com/product/AM62A7#cad-cae-symbols
Ordering & quality
https://www.ti.com/product/AM62A7#order-quality
Package pad diameter and substrate pad dimension
AM62A7 / AM62A7-Q1 -> AMB pkg : ball diameter 0.5mm : substrate pad 0.45mm
The recommendation is 1:1 ratio between PCB pad and substrate pad.
DDR Board Design and Layout Guidelines
AM62Ax DDR Board Design and Layout Guidelines (ti.com)
Escape Routing for PCB Design
AM62Ax Escape Routing for PCB Design
Design Simulation files
https://www.ti.com/product/AM62A7#design-tools-simulation
Simulation files provided includes IBIS, IBIS-AMI, BSDL, Thermal model, power-estimation tool (PET) and SK-AM62A-LP Design File Package (Assembly drawing).
AM62Ax PDN Target impedance values:
| Voltage Rail | Freq Range | Target Impedance (mOhms) |
| VDD_CORE (0.75V) | Low (< 1MHz) | 7.0 |
| Mid (1 - 20 MHz) | 11.7 | |
| High (20 - 50 MHz) | 23.4 | |
| VDD_CORE (0.85V) | Low (< 1MHz) | 6.9 |
| Mid (1 - 20 MHz) | 11.4 | |
| High (20 - 50 MHz) | 22.9 | |
| VDD_DDR (1.1V) | Low (< 1MHz) | 104.5 |
| Mid (1 - 20 MHz) | 174.2 | |
| High (20 - 50 MHz) | 348.3 |
Note: We do not include Buck output inductance in PDN simulations.
Power Distribution Networks: Implementation and Analysis
Sitara Processor Power Distribution Networks: Implementation and Analysis (Rev. F)
High Speed Board design and Signal integrity simulation
https://www.ti.com/lit/an/spraar7i/spraar7i.pdf
https://www.ti.com/lit/an/spracn9d/spracn9d.pdf
SYSCONFIG
DDR subsystem register configuration tool
Technical Documents
Collaterals and app notes
https://www.ti.com/product/AM62A7#tech-docs
Technical Support
AM62A7 / AM62A7-Q1 Custom board design - FAQs
Previous E2E threads - Keywords AM62Ax, AM62A7, AM62A7-Q1
Starting a new thread
Useful links
Notes
