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[FAQ] AM62A7 or AM62A3 Custom board hardware design – Processor DDR Subsystem and Device Register configuration

Other Parts Discussed in Thread: AM62P, AM625, AM623, AM625-Q1, AM62P-Q1, SYSCONFIG

Hi TI Experts,

Could you explain the configurations that are required to be done for the below use cases?

  1. Device used in the EVM is used.
  2. A new functionally compatible device is selected.
  3. Do the above guidelines apply for AM64x, AM625, AM625-Q1, AM623, AM62P and AM62P-Q1 devices?
  • Hi Board designers, 

    Please refer below:

    Device on the EVM is used

    if you used the same device as on the EVM, you can use the same configuration file that comes with the SDK. 

    The only changes that you would possibly need to make is with the termination and drive strength values for both the memory and controller.

    This will depend on your board layout, fab materials, and routing.  Ideal values would have come from board level signal integrity simulations. 

    The sysconfig tool will provide default skew compensation that is used by the controller/PHY during training.

    During DDR initialization and training, these will be optimized by the training sequence of the PHY.

    There aren't any parameters that have to be set in the sysconfig tool


    Alternate (functionally compatible) device is selected.

    In case an alternative, functionally compatible device is selected, a new config file is required to be generated.

    If you need a config file for a different device, you need to generate that with the DDR Register Configuration tool

    The DDR controller and PHY have a large amount of parameters to configure, so to facilitate the configuration, we provide an online tool which generates an output file that is consumed by the driver.

    Access sysconfig tool

    Choose DDR Subsystem Register Configuration in the Software Product menu and choose the required processor - AM62Ax.

    Configure Memory

    This tool takes system information, timing parameters from DDR datasheet, and IO parameters as inputs and then outputs a header file

    which the driver uses to program the DDR controller and PHY. The driver then kicks off the full training sequence.

    Do the above guidelines apply for AM64x, AM625, AM625-Q1, AM623, AM62P and AM62P-Q1 devices?

    It is Ok to follow the described guidelines/recommendations for the above-mentioned devices.