TMS320VC5441 McBSP Clock Question

David Johnson52005

Other Parts Discussed in Thread: TMS320VC5441

I have a customer with multiple designs using the TMS320VC5441. For all designs they have, the core clock that is connected to the DSP is 66mhz. Per the original data sheet the customer used, it states that the minimum cycle time for the clock is 15ns, or 66.666 MHz max. My customer has noticed that on the current data sheets states 20ns or 50MHz is the maximum.

In all of the customers designs the clock in internally divided by 2 for a clock out rate of 132MHz. According to the latest data sheet they are still within that spec--ie minimum cycle time is 7.5ns or 133.33MHz.

The customer has been using the VC5441 with the core clock frequency of 66MHz in many designs for a long time, ie >5yrs. They would like to know what the risk are, if any, to continue running the device with a core clock of 66MHz?

over 12 years ago

0 Hyun Kim over 12 years ago

TI__Genius 14965 points

Hi,

There is a VC5441 Silicon Errata http://focus.ti.com/lit/er/sprz190b/sprz190b.pdf explaining 133-MHz Performance at Page 9. What is CPU supply voltage they use?

Regards,

Hyun

0 David Johnson52005 over 12 years ago in reply to Hyun Kim

Prodigy 60 points

Hyun,

the customer is using 1.6v. the originally used 1.5v but the revised data sheet recommends 1.6v for 133mhz so they are now using 1.6v.

They want to know if running at this speed presents any long term reliability issues.

Dave

0 Hyun Kim over 12 years ago in reply to David Johnson52005

TI__Genius 14965 points

Dave,

Since 1.6V is CVDD norminal voltage, it should be backed by TI's normal reliability range.

http://focus.ti.com/lit/ds/symlink/tms320vc5441.pdf at Page 64

Regards,

Hyun

0 David Johnson52005 over 12 years ago in reply to Hyun Kim

Prodigy 60 points

Hyun,

Is the fact that they use a 66mhz input clock an issue since the data sheet shows a max input clock frequency of 50mhz. They have been using the device this way for over 5 years. The original spec had stated 66mhz max for an input clock then revised data sheet changed to 50mhz max input clock.

Are there any known reliability issues that can be created by doing this or other cautions TI would offer?

Thanks

Dave

0 Hyun Kim over 12 years ago in reply to David Johnson52005

TI__Genius 14965 points

Hi David,

We don't have any reliability issues regarding this. Can you tell what application is this?

Regards,

Hyun

0 David Johnson52005 over 12 years ago in reply to Hyun Kim

Prodigy 60 points

Hyun,

the application is telecom. They acutally by this as TNETV2840 and use the Tellinovations Echo Cancellers they license from us. Echo Cancellation for DSL/POTS line cards.

Does your reply stating "We don't have any reliabiltiy issues regarding this" mean that TI is not aware of any reported problems in the past they would indicate it would effect reliability or are you saying that running the core with a 66mhz input clock frequency is acceptable and will not create reliabilty issues. they have been using it this way for some time and they do not have any evidence of problems.

Dave

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TMS320VC5441 McBSP Clock Question