I have a customer with multiple designs using the TMS320VC5441. For all designs they have, the core clock that is connected to the DSP is 66mhz. Per the original data sheet the customer used, it states that the minimum cycle time for the clock is 15ns, or 66.666 MHz max. My customer has noticed that on the current data sheets states 20ns or 50MHz is the maximum.
In all of the customers designs the clock in internally divided by 2 for a clock out rate of 132MHz. According to the latest data sheet they are still within that spec--ie minimum cycle time is 7.5ns or 133.33MHz.
The customer has been using the VC5441 with the core clock frequency of 66MHz in many designs for a long time, ie >5yrs. They would like to know what the risk are, if any, to continue running the device with a core clock of 66MHz?