PROCESSOR-SDK-DRA7X: Separate Pixel-clock needed for VOUT2/LCD2(LVDS-Out-1) and VOUT3/LCD3(LVDS-Out-2) displays.

Hi,

Sorry, could not figure out from the above code what's changed. could you point me? I would request to refer to TRM and check for possible input clock source for all outputs, driver will support all of them using platform API.

Regards,

Brijesh

Hi Brijesh,

Thanks for your response. As i understand, the pixel-clock-frequency and the clock-source are 2 totally separate things.

1. Main Issue with Pixel-clock-frequency : The issue we are having is that, even though we are setting pixel-clock frequency value of 25.4Mhz for LCD2 and 89.4 Mhz for LCD3, what we are seeing is that both LCD2 & LCD3 are getting set at 25.4MHz. Can you please let us know how/which register value to check on the target to confirm what are the actual pixel-clock frequency values that are set on the target HW for LCD2 & LCD3?

I have tried to check in the TRM as to which register's value to be checked to verify/confirm the pixel-clock frequency values that are set on the target for LCD2 & LCD3. But i am not able to find any specific answer. I checked the section 11.2.4.13.8 DISPC Timing Generator and Panel Settings. It mentions as shown below:

"The 8-bit pixel clock divider (the DISPC_DIVISORo[7:0] PCD bit field) selects the pixel clock frequency.
This bit field generates a range of pixel clock frequencies from LC/2 to LC/256, where LC is the logic clock
from the divided functional clock of the DISPC by the DISPC_DIVISOR[23:16] LCD bit field.
The pixel clock is defined by the following equation:
Pixel Clock = (FunctionalClock/LCD[7:0])/PCD[7:0]"

I am still not clear as to which value of what register I have to check on the target. I also checked section 11.2.4.10.4.2 DISPC Scaling limitations but could not get a clarity.

2. Clock-source: For other single display variants, we had moved from clock-source BSP_PLATFORM_PLL_VIDEO1( BSP_PLATFORM_CLKSRC_DPLL_VIDEO1_CLKOUT3) to clock-source BSP_PLATFORM_CLKSRC_DPLL_HDMI as it was mentioned to be more reliable. Is this change required in this dual-display variant where we are still using the clock-source BSP_PLATFORM_PLL_VIDEO1 for both LCD2 & LCD3?

Regards,

Ameet Sangamkar

(Harman)

Here's What's changed :

Earlier both LCD2 and LCD3 were configured with same timing values like Pixel-clock, HFP, HBP, HSyncLength, VFP, VBP, VSyncLength etc because both were connected to 2 similar displays of 800*480 res.

But now we need to change the configuration of LCD3 to a 1280*720 resolution display with different timings values. While we are able to see other values being set properly, the pixel-clock is not getting set with the 2 different values we have tried till now i.e. 74.25MHz and 89.4 Mhz.Therefore the mentioned source-code and logs may have either of these 2 values for LCD3.

Hope this clarifies the change. More info below:

We have tried testing with 2 sets of display timing values for LCD3:

1. For experimental testing a 1920*720 display where only 1280 pixels are active and rightmost 640 pixels are inactive horizontally :

        pVInfo->mInfo.pixelClock                =   89400u;
        pVInfo->mInfo.fps                       =   60U;
                                                            // HSync Expected Value= ~18.05 KHz
        pVInfo->mInfo.hFrontPorch               =   32u;
        pVInfo->mInfo.hBackPorch                =   63u;
        pVInfo->mInfo.hSyncLen                  =   32u;
                                                            // VSync Expected Value= ~17Hz
        pVInfo->mInfo.vFrontPorch               =   5u;
        pVInfo->mInfo.vBackPorch                =   2u;
        pVInfo->mInfo.vSyncLen                  =   1u;

   Here the display works properly, but we are not sure if the pixel-clock is actually set to 89.4Mhz(and , HSync & VSync values similarly). We are not able to measure these values using oscilloscope on the display in this HW setup.

2. For the actual requirement of a 1280*720 display with values shown below:

        pVInfo->mInfo.pixelClock                =   74250u;  // =====> Actual value recorded on oscilloscope = 25400u; 25.4Mhz
        pVInfo->mInfo.fps                       =   60U;
                                                        // Hsync: Expected Value=45kHz; ====> Actual value recorded on oscilloscope=15.39kHz
        pVInfo->mInfo.hFrontPorch               =   110u;
        pVInfo->mInfo.hBackPorch                =   220u;
        pVInfo->mInfo.hSyncLen                  =   40u;  
                                                        // Vsync Expected Value=60Hz; ====> Actual value recorded on oscilloscope=20.53Hz
        pVInfo->mInfo.vFrontPorch               =   5u;
        pVInfo->mInfo.vBackPorch                =   20u;
        pVInfo->mInfo.vSyncLen                  =   5u;

Here we are seeing a zoomed view of the expected video/graphics content and the values measured for only the pixel-clock, HSync & VSync on the oscilloscope are not as expected and are the same as the values set for LCD2.

Please find below few register values i have read on the target.

/////////////////////////////////   LCD3 - Passenger display  1280*720
DISPC_SIZE_LCD3 (Passenger-Zone)
omapconf read 0x58001834 02CF04FF=0010110011110000010011111111            Lines per panel(height)=719+1 = 720                Pixels per line(width)=1279+1 = 1280
DISPC_TIMING_H3 (HSYNC LCD3)
omapconf read 0x58001840 0DB06D27=1101101100000110110100100111          HBackP=220        HFrontP=110    HSyncWidth=40
DISPC_TIMING_V3 (VSYNC LCD3)
omapconf read 0x58001844 01400504= 00010100 000000000101 00000100        VBackP=20        VFrontP=5    VSyncWidth=4
DISPC_DIVISOR3
omapconf read 0x58001838 00010001=0001 0000 0000 0000 0001              LCD=1       PCD=1

mInfo->pixelClock is just for the information purpose. It is used in the driver to set some register, so you will not find it in some register nor it will change the PLL. 

There is a separate API to configure PLL and also separate APIs to change the clock source for LCD output. 

Regards,

Brijesh

Simple query: How do we set different pixel-clocks for LCD2 & LCD3? Is this relate to PLL & clock source for LCD output? We are using VisionSDK 03_04 version.

Ameet,

As i mentioned earlier, you need to set pixel clock in PLL and set the clock source for LCD2 and LCD3 as one of these PLL. So yes, clock source and PLL are related and there are platform APIs available in the PDK and vision sdk to set them.

Regards,

Brijesh

Hi Brijesh,

Many thanks for the confirmation.

Currently for both LCD2 & LCD3 we are using BSP_PLATFORM_PLL_VIDEO1 and clock-source as BSP_PLATFORM_CLKSRC_DPLL_VIDEO1_CLKOUT3.

As per your comment, do we need to use different PLLs for LCD2 & LCD3 and set corresponding clock-sources like shown below?

LCD2 : Use BSP_PLATFORM_CLKSRC_DPLL_VIDEO1 and corresponding clock-source like BSP_PLATFORM_CLKSRC_DPLL_VIDEO1_CLKOUT3

LCD3 : Use BSP_PLATFORM_CLKSRC_DPLL_VIDEO2 and corresponding clock-source like BSP_PLATFORM_CLKSRC_DPLL_VIDEO2_CLKOUT3.

Regards,

Ameet S

So the confusion is whether it is possible to use 2 different PLLs like BSP_PLATFORM_CLKSRC_DPLL_VIDEO1  for LCD2 and BSP_PLATFORM_CLKSRC_DPLL_VIDEO2  for LCD3 using the API Bsp_platformSetPllFreq(&vPllCfg); This API does not seem to be Venc specific.

Bsp_PlatformSetPllFreq vPllCfg;

vPllCfg.videoPll = BSP_PLATFORM_PLL_VIDEO1;

vPllCfg.chooseMaxorMinMN = (UInt32) BSP_PLATFORM_VIDEO_PLL_CALC_MAX_MN;
status = Bsp_platformSetPllFreq(&vPllCfg);
UTILS_assert (status == SYSTEM_LINK_STATUS_SOK);

Secondly when i try to use BSP_PLATFORM_PLL_VIDEO2 for LCD3 we are getting an error in API Bsp_platformSetVencClkSrc(&vencClkCfg) about clock source BSP_PLATFORM_CLKSRC_DPLL_VIDEO2_CLKOUT3 being invalid:

    if(SYSTEM_DCTRL_DSS_VENC_LCD2 == vencId)
            vPllCfg.videoPll = BSP_PLATFORM_PLL_VIDEO1;
    if(SYSTEM_DCTRL_DSS_VENC_LCD3 == vencId)
            vPllCfg.videoPll = BSP_PLATFORM_PLL_VIDEO2;

switch(vencId)
{

case SYSTEM_DCTRL_DSS_VENC_LCD2:
        vencClkCfg.outputVenc = BSP_PLATFORM_VENC_LCD2;
        vencClkCfg.vencClkSrc = BSP_PLATFORM_CLKSRC_DPLL_VIDEO1_CLKOUT3;
        break;

case SYSTEM_DCTRL_DSS_VENC_LCD3:
        vencClkCfg.outputVenc = BSP_PLATFORM_VENC_LCD3;
        vencClkCfg.vencClkSrc = BSP_PLATFORM_CLKSRC_DPLL_VIDEO2_CLKOUT3;
        break;

default:        UTILS_assert((Bool)0U);
                    break;

}

     Vps_printf("\nDISPLAYCTRL: DisplayCtrlLink_configureVideoPllAndClkSrcForLCD B4 Bsp_platformSetVencClkSrc() vencId=%u, vPllCfg.pixelClk=%u!!!\n",vencId, vPllCfg.pixelClk);

   status = Bsp_platformSetVencClkSrc(&vencClkCfg);
    UTILS_assert (status == SYSTEM_LINK_STATUS_SOK);

LOGS:

[0][      0.655] DISPLAYCTRL: DisplayCtrlLink_configureVideoPllAndClkSrcForLCD B4 Bsp_platformSetVencClkSrc() vencId=4, vPllCfg.pixelClk=74250!!!
[0][      0.655]      1.027328 s: src/bsp_platformTda2xx.c @ Line 286:      1.027481 s: clock source not valid
[0][      0.656]      1.027633 s:  Assertion @ Line: 643 in displayCtrlLink_drv.c: status == SYSTEM_LINK_STATUS_SOK : failed !!!
[0][      0.656]  Assertion @ Line: 643 in displayCtrlLink_drv.c: status == SYSTEM_LINK_STATUS_SOK : failed !!!

root@mmt2020-a880:~# omapconf read 0x58000040
00010000
root@mmt2020-a880:~# omapconf read 0x4A002538
000002A8
root@mmt2020-a880:~#

Hi Ameet,

Ameet Sangamkar said:

As per your comment, do we need to use different PLLs for LCD2 & LCD3 and set corresponding clock-sources like shown below?

Yes, if your resolution requirement is different, you do require different PLL for both the outputs.

Ameet Sangamkar said:

So the confusion is whether it is possible to use 2 different PLLs like BSP_PLATFORM_CLKSRC_DPLL_VIDEO1  for LCD2 and BSP_PLATFORM_CLKSRC_DPLL_VIDEO2  for LCD3 using the API Bsp_platformSetPllFreq(&vPllCfg); This API does not seem to be Venc specific.

Yes, you need to use this API to first the PLL output.

Ameet Sangamkar said:

Secondly when i try to use BSP_PLATFORM_PLL_VIDEO2 for LCD3 we are getting an error in API Bsp_platformSetVencClkSrc(&vencClkCfg) about clock source BSP_PLATFORM_CLKSRC_DPLL_VIDEO2_CLKOUT3 being invalid:

Could you please refer to TRM for possible PLLs for LCD3 output? If not Video2, you could possibly use HDMI PLL for LCD3.

Also please check from where this error "clock source not valid" is coming. You might just require to update this API if TRM says it is supported. 

Regards,

Brijesh 

Hi Brijesh,

Thanks for your suggestions. In other tickets https://e2e.ti.com/support/processors/f/791/t/860813#pi320966=2 & https://e2e.ti.com/support/processors/f/791/t/889397, earlier we had done similar change to use HDMI PLL for LCD2 in a different single-display variant. I will try to do the same for LCD3 here.

[0][      0.655] DISPLAYCTRL: DisplayCtrlLink_configureVideoPllAndClkSrcForLCD B4 Bsp_platformSetVencClkSrc() vencId=4, vPllCfg.pixelClk=74250!!!
[0][      0.655]      1.027328 s: src/bsp_platformTda2xx.c @ Line 286:      1.027481 s: clock source not valid

The above error about invalid clock source was coming from src/bsp_platformTda2xx.c after calling Bsp_platformSetVencClkSrc as shown below when trying to use VIDEO2 PLL and BSP_PLATFORM_CLKSRC_DPLL_VIDEO2_CLKOUT3 LCD3.

    if(SYSTEM_DCTRL_DSS_VENC_LCD3 == vencId)
    {
    vPllCfg.videoPll = BSP_PLATFORM_PLL_VIDEO2;
    }

    case SYSTEM_DCTRL_DSS_VENC_LCD3:
        vencClkCfg.outputVenc = BSP_PLATFORM_VENC_LCD3;
        vencClkCfg.vencClkSrc = BSP_PLATFORM_CLKSRC_DPLL_VIDEO2_CLKOUT3;

status = Bsp_platformSetVencClkSrc(&vencClkCfg);

But as you mentioned, first I need to enable the HDMI PLL from LCD3_CLK and get the below mentioned config in DSS_CTRL. Then i can use clock source BSP_PLATFORM_CLKSRC_DPLL_HDMI to avoid this error.

LCD3_CLK_SWITCH -> DPLL_DSI1_C_CLK1 selected

DSI1_C_CLK1_SELECTION -> HDMI selected.

Regards,

Ameet S