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TDA4VE-Q1: MMC layout guidelines

Part Number: TDA4VE-Q1

Dear expert

Our customer is doing PCB layout. Do we have eMMC and SDIO layout guidelines? I cannot find that in Jacinto 7 High-Speed Interface Layout Guidelines.

If not have, is there any layout advice for customer (impedance, equal-length...)? Thanks.

Best Regards,

Xingyu Zhu

  • Hi Xingyu,

    The SD and JEDEC industrial specifications provide guidelines on electrical and mechanical connections of the card
    and controller for reliable operation. You must follow these guidelines to ensure proper functionality.
    TI offers a schematic checklist as well. For more information on the checklist – or to submit your board layout
    files for review with TI – approach your local Field Application Engineer to understand the review submission

    A few of the recommended signal integrity best practices include:
    • Separate routing layers with GND layers.
    • Avoid gaps in ground plane between source and load.
    • Wherever a signal goes through a via, have a return GND via very close (within a few mm).
    • Avoid cross-talk/coupling. Do not route two signals directly above or below each other.
    • Avoid cross-talk/coupling. Route traces with spaces between traces that are 2-3X the trace width.
    • Avoid stubs. Have zero stubs on traces.
    • Ensure signals are monotonic at inputs
    • Ensure impedance match