SK-AM62A-LP: How the PMIC_LPM_EN0 works

Zehui Li

Part Number: SK-AM62A-LP
Other Parts Discussed in Thread: SYSCONFIG

According to the figure, PMIC_LPM_EN0 is default low after reset. J9=floating，for U31, SEL=1，A=A1=PMIC_LPM_EN0=low, why PMIC don't switch to OFF state since enable/nPWRON PIN gets LOW. Is the PMIC configured in First Supply Detection (FSD) mode during power-up? Is GPIO3 configured as NSLEEP PIN for default，or the NSLEEP1B and NSLEEP2B register bits are configured in place for the function. If GPIO3 is configured as NSLEEP PIN for default, which one has been chosen? NSLEEP1 or NSLEEP2.

over 1 year ago

0 Kallikuppa Sreenivasa over 1 year ago

TI__Guru** 123868 points

Hello Zehui Li

Thank you for the query.

Let me reassign to the PMIC expert to answer your questions.

Regards,

Sreenivasa

0 David Martinez over 1 year ago in reply to Kallikuppa Sreenivasa

TI__Intellectual 1921 points

Hi.

Sorry for the delay. There are many inquiries for this device right now. Please expect a response later this week.

Best,

David Martinez

0 Brenda Diaz over 1 year ago in reply to David Martinez

TI__Genius 15875 points

Hi,

As noted in the AM62A datasheet the PMIC_LPM_EN0 signal is a dual-function PMIC control output. It triggers the low power mode (active low) or enables the PMIC (active high). The connection of this signal to the PMIC will depend on the processor low power mode that is used on the application.

PMIC_LPM_EN0 drives the TPS65931211-Q1 enable pin when using Partial IO low power mode.
PMIC_LPM_EN0 drives the TPS65931211-Q1 GPIO3 (nSLEEP2) when using IO+DDR low power mode.

From AM62A data sheet:

Thanks,

Brenda

0 Zehui Li over 1 year ago in reply to Brenda Diaz

Intellectual 380 points

Hi Brenda，

Thanks for your reply.

"PMIC_LPM_EN0 drives the TPS65931211-Q1 enable pin when using Partial IO low power mode."------The PMIC will go into Partial IO LP mode by driving enable pin LOW because NVM sets LP_STANDBY_SEL BIT=1 by default. Do I understand correctly?

What really confuse me is not only the function itselt. I am confused by the state of PMIC_LPM_EN0 after reset because TI FEA told me it was default low. So accordding to what I said above "J9=floating，for U31, SEL=1，A=A1=PMIC_LPM_EN0=low" and your reply, the PMIC will go to LP mode. However what we expect is to work in normal mode.

0 David Martinez over 1 year ago in reply to Zehui Li

TI__Intellectual 1921 points

Hi.

Brenda is currently out of office. She'll be back tomorrow to review your inquiries.

Sorry for the delay.

Best,

David Martinez

+1 Brenda Diaz over 1 year ago in reply to Zehui Li

TI__Genius 15875 points

Hi,

"Partial IO" is a low power mode on the AM62A processor and it is independent from the LP_STANDBY_SEL bit on the PMIC. PMIC_LPM_EN0 is high by default (using the external pull-up resistor). See the AM62A technical reference manual (AM62Ax Sitara Processors Technical Reference Manual (Rev. A)) for more information about each of the low power modes supported on the AM62A processor.

PMIC_LPM_EN0 drives the TPS65931211-Q1 enable pin when using AM62A Partial IO low power mode.
- when EN pin is high, PMIC is in active state (rails ON)
- when EN pin is low, PMIC executes an orderly power-down and transitions to Standby State (rails OFF)

PMIC_LPM_EN0 drives the TPS65931211-Q1 GPIO3 (nSLEEP2) when using AM62A IO+DDR low power mode.
- when PMIC GPO3 is high, PMIC is in active state (rails ON)
- when PMIC GPO3 is low, PMIC turns-OFF all rails except Buck4 (VDDS_DDR) and Buck5 (DVDD1V8). The PMIC GPIO4 also stays high to keep the external 3.3V load switch enabled.

Thanks,

Brenda

0 Zehui Li over 1 year ago in reply to Brenda Diaz

Intellectual 380 points

Hi，

Thanks for reply.

I read the TRM. So the Partial IO Low Power mode shuts down the PMIC except the always-on power of CANUART.

How do I know the state of PINs after reset when they choose pinmux? FEA told me to follow the table of EVM SCH, but it's different from what you said.

0 Brenda Diaz over 1 year ago in reply to Zehui Li

TI__Genius 15875 points

Hi,

Yes, for Partial IO, all the PMIC rails are turned-OFF. Only the external discrete supplying VDDSHV_CANUART and VDD_CANUART are kept ON. I will re-assign this E2E to the processor team so they can provide more information on the default and reset state of the PMIC_LPM_EN0.

Thanks,

Brenda

+1 Senthilkumar Srinivasan over 1 year ago in reply to Zehui Li

TI__Mastermind 43660 points

Hello Zehui,

There is a bug in the GPIO mapping table in the schematics. After RESET, the PMIC_LPM_EN0 default to logic high to enable the PMIC. You may need to refer EVM SysConfig file to understand the default logic of all the IOs.

Regards,
Senthil

0 Zehui Li over 1 year ago in reply to Senthilkumar Srinivasan

Intellectual 380 points

Hi，

Thanks.

Where could I find this EVM SysConfig file?Could you send one?Or I have to contact my FEA to get it?

0 Senthilkumar Srinivasan over 1 year ago in reply to Zehui Li

TI__Mastermind 43660 points

Hello Zehui,

I would prefer to contact FAE.

Rergards,
Senthil

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SK-AM62A-LP: How the PMIC_LPM_EN0 works