With reference to the linked question, although it appears that the change suggested by Ashwani Goel has been incorporated into the latest SDK (my version of the file does show a value of 4), something is still amiss.
I am using an AM64B board and running the ./mcu_plus_sdk_am64x_08_05_00_24/tools/boot/sbl_prebuilt/am64x-sk/sbl_null.release.hs_fs.tiimage image (MD5: 9890891082c94b5b5778322229ae600c).
This is the example I have imported:
The example fails with, as far as I can tell, the same exact error as that in the linked question:
==========================
Layer 2 CPSW Test
==========================
Init all peripheral clocks
----------------------------------------------
Enabling clocks!
Create RX tasks
----------------------------------------------
cpsw-3g: Create RX task
Open all peripherals
----------------------------------------------
cpsw-3g: Open enet
EnetAppUtils_reduceCoreMacAllocation: Reduced Mac Address Allocation for CoreId:1 From 4 To 3
Init all configs
----------------------------------------------
cpsw-3g: init config
Mdio_open: MDIO Manual_Mode enabled
EnetRm_open: Resource partition validation failed: -3
EnetMod_open: cpsw3g.rm: Failed to open: -3
Cpsw_openInternal: Failed to open RM: -3
Assertion @ Line: 984 in /home/gtbldadm/nightlybuilds/mcupsdk_internal/jenkins/mcu_plus_sdk_am64x_08_05_00_24/source/networking/enet/core/src/per/V1/cpsw.c: hCpsw->hRxRsvdFlow != NULL
There are working Ethernet cables connected to both interfaces; I did try all possible combinations to no avail.
I am a bit at a loss here and would appreciate any ideas on where to go from here.
