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SK-TDA4VM: Does TI modify the internal EEPROM of the CDCI6214 clock generator used on SK-TDA4VM?

Part Number: SK-TDA4VM

Hi there,

The SK-TDA4VM utilizes the same clock generator for PCIe as the J7EVM common processor board, but it is configured to run from EEPROM page 0 (EEPROMSEL = low).

EEPROM page 0, if the default EEPROM contents are present, would put the device into pins mode, where the I2C bus SCL/SDA signals become OE for clocks 2 and 3.

In this case, if I read the datasheet correctly, transactions on i2C0 would interrupt the clocks outputs for clock outputs 2 and 3.

Does TI program a different EEPROM setting into this part?

  • Yes - this is an error in the SK-TDA4VM design.  Any activity on I2C0 will cause the CDCI clock outputs to enable/disable.  Resistors R385, R387 should be removed from the design to isolate the I2C0 from CDCI device, and those CDCI pins should be pulled up (if not done so internally by the CDCI device).

  • Hi Robert,

    Thanks for confirming! Yes - the SCL/SDA signals do not have internal weak pullups (so as to not interfere with external I2C strong pullups), but the other OE signals do. So external pullups are going to be needed.

    In any case, thanks very much for checking on it!