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Unable to load PRU firmware from CCS to EVM HS-FS board

Part Number: PROCESSOR-SDK-AM64X


Hi, my goal is to load and run custom software on a PRU core of an AM64xx EVM HS-FS board from CCS.  I'm not able to load code to the PRU. Could someone help me do this?



Here's what I've tried so far and how its failed:

I've been following the PRU Getting Started Labs.
I'm failing to load the PRU firmware in Step 4:.

When I try to connect to the DMSC core to set up the PRU core clock so CCS can connect to the PRU, CCS fails with the following error message:


Error connecting to the target:
(Error -1170 @ 0x0)
Unable to access the DAP. Reset the device, and retry the operation. If error persists, confirm configuration, power-cycle the board, and/or try more reliable JTAG settings (e.g. lower TCLK).
(Emulation package 9.10.0.00080)


I think this fails because I'm using an HS-FS board.
I've tried following the "Application boot using CCS + GELs" solution from the HS-FS migration guide.

When I get to the "Run the load_dmsc_hs_fs.js script from the scripting console", the script fails.
I see the following output in the Console:



MAIN_Cortex_R5_0_0]
DMSC Firmware Version 8.5.3--v08.05.03 (Chill Capybar
DMSC Firmware revision 0x8
DMSC ABI revision 3.1

[SCICLIENT] ABI check PASSED
[SCICLIENT] Board Configuration with Debug enabled ...
[SCICLIENT] Common Board Configuration PASSED
[SCICLIENT] PM Board Configuration PASSED
[SCICLIENT] RM Board Configuration PASSED
[SCICLIENT] Security Board Configuration PASSED

DMSC Firmware Version 8.5.3--v08.05.03 (Chill Capybar
DMSC Firmware revision 0x8
DMSC ABI revision 3.1

Starting SOC Initialization ...
Resetting self cluster...


and then the following error message in the Console:



MAIN_Cortex_R5_0_0: GEL Output: Running from M3
MAIN_Cortex_R5_0_0: Error: (Error -1141 @ 0x1FE) Device is not responding to the request. Reset the device, and retry the operation. If error persists, confirm configuration, power-cycle the board, and/or try more reliable JTAG settings (e.g. lower TCLK). (Emulation package 9.10.0.00080)
MAIN_Cortex_R5_0_0: Trouble Halting Target CPU: (Error -2062 @ 0x136) Unable to halt device. Reset the device, and retry the operation. If error persists, confirm configuration, power-cycle the board, and/or try more reliable JTAG settings (e.g. lower TCLK). (Emulation package 9.10.0.00080)


When I try continuing the R5 program and connecting to a PRU core, CCS continually hangs while "Connecting".

I've tried decreasing the JTAG TCLK setting to the minimum (100kHz); this script still fails in the same way.

  • Hello Andy,

    I am not a PRU expert. But I think I can help you connecting to PRU core.

    Please refer to the below linked response

    https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1196054/processor-sdk-am64x-error-to-connect-to-a53-or-m4f-by-ccs/4537640#4537640

    The above response suggests a solution for enabling DDR. However, you can add PRU instead of DDR as shown below and then the remaining steps are the same.

    I am also attaching the updated sciclient_ccs_init example with PRU enabled for reference

    sciclient_ccs_init.zip

    After following the above steps, you should be able to connect to PRU core as shown in the below screen recording

    Let me know if the above helps.

    Regards,

    Prashant

  • Thank you Prashant, this was very helpful. I'm able to connect to the PRU core through CCS and debug now.