AM6442: How to set the current Timestamp in Application and Real time core's.

We have connected AM6442 to wifi AP, can able to ping to google.com. How to installed ntp in rt-linux and synchronize the time stamp of the board?

following below link to download ntp protocol on the TI board AM64x

https://e2e.ti.com/support/processors-group/processors/f/processors-forum/646368/linux-ffmpeg-install-issue-on-am5728-evm/2374626#2374626

While downloading the git repo in HOST environment it aborts.

Hi Venkata,

nptd (via Yocto package openntpd) is part of the default SD card images for our AM6x devices, see below example of an AM62x "default" image. So it should be readily available and setup to go.

$ tar -tvf arago-tmp-default-glibc/deploy/images/am62xx-evm/tisdk-default-image-am62xx-evm.tar.xz | grep \/ntp
-rw-r--r-- 0/0             409 2023-03-03 13:11 ./etc/ntpd.conf
drwxr-xr-x 0/0               0 2023-03-03 12:57 ./lib/systemd/ntp-units.d/
-rw-r--r-- 0/0              26 2023-03-03 12:36 ./lib/systemd/ntp-units.d/80-systemd-timesync.list
\-rwxr-xr-x 0/0           43752 2023-03-03 13:11 ./usr/sbin/ntpd

Can you confirm /usr/sbin/ntpd is installed on your system and running (via `ps')?

Regards, Andreas

venkata swamy kassa said:

following below link to download ntp protocol on the TI board AM64x

https://e2e.ti.com/support/processors-group/processors/f/processors-forum/646368/linux-ffmpeg-install-issue-on-am5728-evm/2374626#2374626

While downloading the git repo in HOST environment it aborts.

The correct Yocto setup instructions for our current AM64 TI SDK v8.6 are documented here: https://software-dl.ti.com/processor-sdk-linux/esd/AM64X/08_06_00_42/exports/docs/linux/Overview_Building_the_SDK.html

Note that the instructions no longer contain a reference to the arago-project.org server. This server was retired, and the respective repositories are now hosted at https://git.ti.com/cgit/arago-project/. Just follow the build instructions above and that's all you should need to setup & build filesystem images.

Regards, Andreas

Thanks Andreas for the information.

We want to use the PTP(precision time protocol) instead of ntp. How to use ptp in TI Am64x.

Also R5 core and A53 core si showing the different time stamp. How to synchronize the both of then to same time stamp.

Hi!

venkata swamy kassa said:

We want to use the PTP(precision time protocol) instead of ntp. How to use ptp in TI Am64x.

Some background on how to setup and use PTP can be found in the AM64x SDK documentation at https://software-dl.ti.com/processor-sdk-linux/esd/AM64X/08_06_00_42/exports/docs/linux/Foundational_Components/Kernel/Kernel_Drivers/Network/CPSW-PTP.html?highlight=ptp   If you have any questions around this topic please open a new E2E thread specifically for PTP.

venkata swamy kassa said:

Also R5 core and A53 core si showing the different time stamp. How to synchronize the both of then to same time stamp.

Is this about sharing the regular (virtual) RTC from Linux with date/time with the R5 core, after it gets set through NTP? (note the AM64x doesn't have a HW RTC peripheral). I suppose if this is what you are asking you could pass the time to the R5 core using some IPC mechanism.

Regards, Andreas

I guess this could help.

https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1187706/am6421-synchronizing-r5f-timer-with-a53-linux-system-time/4476732?tisearch=e2e-sitesearch&keymatch=%20user%3A387520#4476732

Hello Venkata,

Do you need additional assistance here?

Regards,

Nick

Any example code which depicts "the synchronizing R5F timer with Linux system time with CPTS TS_COMP or any other?"

I am reaching out to some other team members. We are also talking with Lawrence about a call.

Regards,

Nick

Hi Nick, 

Lawrence mentioned below step on the time synchronization.

1. Time Sync router documentation: https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1061474/faq-am64x-what-is-the-time-sync-router-for-how-do-i-use-it

2.Sending a PPS signal to an output pin through the time sync router: https://software-dl.ti.com/processor-sdk-linux/esd/AM64X/08_05_00_21/exports/docs/linux/Foundational_Components/Kernel/Kernel_Drivers/Network/CPSW3g.html#common-platform-time-sync-cpts-module

3.Other notes: In order to send a PPS signal through the time sync router to an R5F core, the signal would need to be routed to the Interrupt Aggregator through one of the l2g_event_pend outputs. Then the Interrupt Aggregator could send the signal to the R5F core. At this point in time I am not aware of an example of configuring the Interrupt Aggregator

4. A very initial, non-precise version of time sync could be done by just sending the Linux system time to the R5F core through an RPMsg. Expect an offset of however many 10s of usec it takes for R5F to receive and process the RPMsg

We explored option #1 and We are using the Processor SDK RT-Linux for AM64x SDK version: 08.06.00.42 default image.
We can see from the Boot up log, timesync-router enabled.

[ 0.711407] pinctrl-single a40000.timesync-router: 512 pins, size 2048

Can you please give mores details on how TSR sends interrupt control to R5?

Also During the call we discuss on to try on setting the jumber setting on J3 pin on AM64x. I have tried to set up the jumper on J3 and observed no time synchroniztion happened in R5 and A53. We still see the difference.

A53 Time:

R5 Time:

Hello Venkata,

How does the time sync router work

The basic idea of the time sync router is that it allows for pulses to be sent from one core to another core or cores. If sending to multiple cores, then you know that the pulse is arriving at all locations within just a couple of nanoseconds, as detailed in the FAQ linked in your response. You can think of it like an internal PPS signal going from one core to other places in the processor.

viewing the PPS output signal on J3 

The point is not to put a jumper between the pins on AM64x SK J3, but to connect one of those pins to an oscilloscope to see the PPS output signal. This is NOT doing any synchronization between Linux and R5F. It is just outputting a PPS signal as described in the SDK link in your response.

Synchronizing R5F and Linux

Did you write code to update the R5F counter value after it observes a rising or a falling edge coming from the time sync router? As discussed in 3. and 4. of your response, TI has not currently written an example where we configure the interrupt aggregator so a time sync signal can be routed to R5F, and then update the R5F counter based on a pulse signal from A53.

Regards,

Nick

Hi,

Can you please elaborate in How to observes a rising or a falling edge coming from the time sync router. and which R5F counter needs to be updated here?

Also Can you give us some pointer on how to set time (TimeSetAPI) in R5 , if we can get the time value from A53 through RPMsg.

Thanks,

Venkat

Hello Venkat,

I am sending your thread over to a team member who is more familiar with R5F programming than I am. They can discuss

1) How to get an interrupt from a rising or falling edge signal

2) How to use / update counter values

As discussed earlier, we do not currently have a good software example for how to configure a signal to go from the Time Sync Router --> L2G --> Interrupt Aggregator --> R5F. 

Regards,

Nick

Thanks Nick. Looking forward for the information.

Hello Venkat,

Last time I was talking with Nick, He explained the your requirements, as you need to route time sync event interrupts to L2G and finally to the R5F core.

Are you expecting this solution?

Regards,

S.Anil.

Hi Anil,

Yes, you are right. We are looking for the same. We want to synchronize the time between A53 and R5.

Thanks,

Venkat

Hello Venkat,

Thanks for your input.

I have knowledge on routing IEP comp events to trigger DMA.

So, in a similar way, we can route them for time-synchronized events.

But I can easily help you route TIME SYSNC events to L2G, and finally routing an interrupt to the R5F core is new for me. We have to work with the system team as well since this type of application is not available on MCU+SDK examples and we need to spend time on it.

Can you please confirm which input you want to give to the TIME_SYNC_EVENT_INTRR?

As of now, as per TRM, it can take almost 43 inputs, which are available below.

#define CSLR_TIMESYNC_EVENT_INTROUTER0_IN_TIMER0_TIMER_PWM_0 (0U)
#define CSLR_TIMESYNC_EVENT_INTROUTER0_IN_TIMER1_TIMER_PWM_0 (1U)
#define CSLR_TIMESYNC_EVENT_INTROUTER0_IN_TIMER2_TIMER_PWM_0 (2U)
#define CSLR_TIMESYNC_EVENT_INTROUTER0_IN_TIMER3_TIMER_PWM_0 (3U)
#define CSLR_TIMESYNC_EVENT_INTROUTER0_IN_PINFUNCTION_PRG0_IEP0_EDC_LATCH_IN0IN_PRG0_IEP0_EDC_LATCH_IN0_0 (4U)
#define CSLR_TIMESYNC_EVENT_INTROUTER0_IN_PINFUNCTION_PRG0_IEP0_EDC_LATCH_IN1IN_PRG0_IEP0_EDC_LATCH_IN1_0 (5U)
#define CSLR_TIMESYNC_EVENT_INTROUTER0_IN_PINFUNCTION_PRG0_IEP1_EDC_LATCH_IN0IN_PRG0_IEP1_EDC_LATCH_IN0_0 (6U)
#define CSLR_TIMESYNC_EVENT_INTROUTER0_IN_PINFUNCTION_PRG0_IEP1_EDC_LATCH_IN1IN_PRG0_IEP1_EDC_LATCH_IN1_0 (7U)
#define CSLR_TIMESYNC_EVENT_INTROUTER0_IN_PINFUNCTION_PRG1_IEP0_EDC_LATCH_IN0IN_PRG1_IEP0_EDC_LATCH_IN0_0 (8U)
#define CSLR_TIMESYNC_EVENT_INTROUTER0_IN_PINFUNCTION_PRG1_IEP0_EDC_LATCH_IN1IN_PRG1_IEP0_EDC_LATCH_IN1_0 (9U)
#define CSLR_TIMESYNC_EVENT_INTROUTER0_IN_PINFUNCTION_PRG1_IEP1_EDC_LATCH_IN0IN_PRG1_IEP1_EDC_LATCH_IN0_0 (10U)
#define CSLR_TIMESYNC_EVENT_INTROUTER0_IN_PINFUNCTION_PRG1_IEP1_EDC_LATCH_IN1IN_PRG1_IEP1_EDC_LATCH_IN1_0 (11U)
#define CSLR_TIMESYNC_EVENT_INTROUTER0_IN_PINFUNCTION_CP_GEMAC_CPTS0_HW1TSPUSHIN_CP_GEMAC_CPTS0_HW1TSPUSH_0 (12U)
#define CSLR_TIMESYNC_EVENT_INTROUTER0_IN_PINFUNCTION_CP_GEMAC_CPTS0_HW2TSPUSHIN_CP_GEMAC_CPTS0_HW2TSPUSH_0 (13U)
#define CSLR_TIMESYNC_EVENT_INTROUTER0_IN_PINFUNCTION_CPTS0_HW1TSPUSHIN_CPTS0_HW1TSPUSH_0 (14U)
#define CSLR_TIMESYNC_EVENT_INTROUTER0_IN_PINFUNCTION_CPTS0_HW2TSPUSHIN_CPTS0_HW2TSPUSH_0 (15U)
#define CSLR_TIMESYNC_EVENT_INTROUTER0_IN_CPTS0_CPTS_GENF0_0 (16U)
#define CSLR_TIMESYNC_EVENT_INTROUTER0_IN_CPTS0_CPTS_GENF1_0 (17U)
#define CSLR_TIMESYNC_EVENT_INTROUTER0_IN_CPTS0_CPTS_GENF2_0 (18U)
#define CSLR_TIMESYNC_EVENT_INTROUTER0_IN_CPTS0_CPTS_GENF3_0 (19U)
#define CSLR_TIMESYNC_EVENT_INTROUTER0_IN_CPTS0_CPTS_GENF4_0 (20U)
#define CSLR_TIMESYNC_EVENT_INTROUTER0_IN_CPSW0_CPTS_GENF0_0 (21U)
#define CSLR_TIMESYNC_EVENT_INTROUTER0_IN_CPSW0_CPTS_GENF1_0 (22U)
#define CSLR_TIMESYNC_EVENT_INTROUTER0_IN_PCIE0_PCIE_CPTS_GENF0_0 (23U)
#define CSLR_TIMESYNC_EVENT_INTROUTER0_IN_CPTS0_CPTS_GENF5_0 (24U)
#define CSLR_TIMESYNC_EVENT_INTROUTER0_IN_PRU_ICSSG0_PR1_EDC0_SYNC0_OUT_0 (25U)
#define CSLR_TIMESYNC_EVENT_INTROUTER0_IN_PRU_ICSSG0_PR1_EDC0_SYNC1_OUT_0 (26U)
#define CSLR_TIMESYNC_EVENT_INTROUTER0_IN_PRU_ICSSG0_PR1_EDC1_SYNC0_OUT_0 (27U)
#define CSLR_TIMESYNC_EVENT_INTROUTER0_IN_PRU_ICSSG0_PR1_EDC1_SYNC1_OUT_0 (28U)
#define CSLR_TIMESYNC_EVENT_INTROUTER0_IN_PRU_ICSSG1_PR1_EDC0_SYNC0_OUT_0 (29U)
#define CSLR_TIMESYNC_EVENT_INTROUTER0_IN_PRU_ICSSG1_PR1_EDC0_SYNC1_OUT_0 (30U)
#define CSLR_TIMESYNC_EVENT_INTROUTER0_IN_PRU_ICSSG1_PR1_EDC1_SYNC0_OUT_0 (31U)
#define CSLR_TIMESYNC_EVENT_INTROUTER0_IN_PRU_ICSSG1_PR1_EDC1_SYNC1_OUT_0 (32U)
#define CSLR_TIMESYNC_EVENT_INTROUTER0_IN_PCIE0_PCIE_CPTS_SYNC_0 (33U)
#define CSLR_TIMESYNC_EVENT_INTROUTER0_IN_CPSW0_CPTS_SYNC_0 (34U)
#define CSLR_TIMESYNC_EVENT_INTROUTER0_IN_CPTS0_CPTS_SYNC_0 (35U)
#define CSLR_TIMESYNC_EVENT_INTROUTER0_IN_GTC0_GTC_PUSH_EVENT_0 (36U)
#define CSLR_TIMESYNC_EVENT_INTROUTER0_IN_PCIE0_PCIE_CPTS_HW1_PUSH_0 (37U)
#define CSLR_TIMESYNC_EVENT_INTROUTER0_IN_PCIE0_PCIE_PTM_VALID_PULSE_0 (38U)
#define CSLR_TIMESYNC_EVENT_INTROUTER0_IN_EPWM0_EPWM_SYNCO_O_0 (39U)
#define CSLR_TIMESYNC_EVENT_INTROUTER0_IN_EPWM3_EPWM_SYNCO_O_0 (40U)
#define CSLR_TIMESYNC_EVENT_INTROUTER0_IN_EPWM6_EPWM_SYNCO_O_0 (41U)

Regards,

S.Anil.

Hi Anil,

I don't know exactly which event to be route to sync the time between A53 to R5. May be system team know more details.

May be this event #define CSLR_TIMESYNC_EVENT_INTROUTER0_IN_CPTS0_CPTS_GENF0_0 (16U) will be used.

Thanks,

Venkat

Hello Venkat ,

Typically, we need input ( CSLR_TIMESYNC_EVENT_INTROUTER0_IN_CPTS0_CPTS_GENF0_0) when we route an event to the TIMESYNCH_EVNT_INTR Router.

From my side, I can do the below steps:

1. I can configure the TISCI client configuration to route the above event to L2G.

2. L2G output to IA

3. IA to R5F core - >  We need to spend more time on this.

So, you can integrate these changes in your application and do test testing.

Is this fine? Since I am also not aware of much about networking applications.

Regards,

S.Anil.

That works Anil. Please give us detailed steps on the same.

Ok venkat.

I am working on your request.

I will update the status once I have done .

Regards,

S.Anil.

Hello Venkat ,

Status update : 

Yesterday I started working on routing a TIMESYNCH EVNT INTRRR output to L2G and then finally routing to IA.

But I noticed this approach can only be used in DMA applications. 

So, as per my understanding, we can't route direct time sync events to the destination core with out the DMA application.

It means that the below approach is not possible.

GENF/other events > TIMESYNCH EVNT INTR -> L2G > IA -> R5F core > Not possible 

below approch is possible 

 GENF/other events > TIMESYNCH EVNT INTR -> L2G >DMASS >  IA -> R5F core > possible

I have already sent mail to the system engineer to get information about whether we can route IA to the destination core without a DMA application or not. Once I get a reply from the system engineer, I will update the status.

One more thing: instead of routing time sync events to the R5F core without DMA , we can route them to PRU cores and CPTS modules as per TRM.

This approach is not used in your application. Please read on for more information on Time SYNCH EVEN INTRR.

https://www.ti.com/document-viewer/lit/html/SPRUIM2F/GUID-F3F5A96C-7822-4966-BBA9-7ACF6CFAF12B#GUID-A9EEA5F6-D24B-46C0-BC77-61B104486ECA

Regards,

S.Anil.

Hello Venkat,

Thanks for the patience.

As per the system engineer, we can route Time sync events to R5F through IA, but I have tried multiple times and it is not working.

I tried the below steps to achieve your requirement, but I was failing at the 3rd step.

Swargam Anil said:

1. I can configure the TISCI client configuration to route the above event to L2G.

2. L2G output to IA

3. IA to R5F core - >  We need to spend more time on this.

I need to spend some more time on it, and I have highlighted below the yellow color so we can easily route GENF events to yellow-colored events rather than R5F. If you want to route GENF events to below-highlighted colors , then please let me know so I can share the code.

This method easily work out .

Regards,

S.Anil.