AM6442: How to enable the L1 Cache and L2 Cache ECC Protection on Arm Cortex-A53?

lina zhang

Intellectual 420 points

Part Number: AM6442

Hi, experts:

How to enable the L1 Cache and L2 Cache ECC Protection on Arm Cortex-A53?

Please supply relevant config registers and interrupt register.

Thanks.

Best wishes.

over 1 year ago

0 Mukul Bhatnagar over 1 year ago

TI__Guru* 81725 points

Hi Lina

Can you clarify what OS and SDK you are using for A53? We do not really support bare metal / RTOS programming on A53 cores.

Regards

Mukul

0 lina zhang over 1 year ago in reply to Mukul Bhatnagar

Intellectual 420 points

On U-boot of am64x, how to enable the L1 Cache and L2 Cache ECC Protection on Arm Cortex-A53?

And we are using self-development microkernel OS which has been running on A53 cores.

0 Pekka Varis over 1 year ago in reply to lina zhang

TI__Mastermind 24850 points

The caches on A53 are either on or off with the features enabled in the HW options (https://developer.arm.com/documentation/ddi0500/j/System-Control/AArch64-register-descriptions/L2-Control-Register?lang=en ), you cannot control error correction and detection schemes. AM6442 has the "SCU-L2 cache protection" and "CPU cache protection" options turned on.

So if you have the instruction and unified cache turned on (register https://developer.arm.com/documentation/ddi0500/e/system-control/aarch64-register-descriptions/system-control-register--el3 ) you have all the protections on.

Reporting of detected errors is documented in https://developer.arm.com/documentation/ddi0500/e/cache-protection/error-reporting .

Pekka

0 lina zhang over 1 year ago in reply to Pekka Varis

Intellectual 420 points

Hi，The programming instruction document I am using is AM64x /AM243x Processors Silicon Revision 1.0 Texas Instruments Families of Products，In Chapter 6.1 section describes the Arm® Cortex®-A53 Subsystem (A53SS) in the device,I would like to know a detailed example of the registers described in this chapter，I would like to know the detailed configuration of the registers described in this chapter and how to trigger ECC errors to ensure our configuration is correct.

0 Pekka Varis over 1 year ago in reply to lina zhang

TI__Mastermind 24850 points

The A53 is a standard A53 core revision r0p4 and the rest of the configuration options described in "6.1.3.2 Arm Cortex-A53 Cluster". Details of the core including all registers are in Arm A53 TRM https://developer.arm.com/documentation/ddi0500/latest/ . Specifically error injection sequence is documented in https://developer.arm.com/documentation/ddi0500/j/Cache-Protection/Error-injection .

Pekka

0 Thomas Yang55737 over 1 year ago in reply to Pekka Varis

TI__Expert 4691 points

Hi Pekka,

What customer want is to simulate softbit error and verify whether ECC functionality works well or not, currently TI MCU+ SDK SDL don't have this example, so want to know the why how to simulate ECC verification just like Keystone device ways before, any idea?

-Thomas

0 Pekka Varis over 1 year ago in reply to Thomas Yang55737

TI__Mastermind 24850 points

The above comment still applies for the standard A53 error injection. In MCU+ SDK 8.6 (should be out within a week or so) we will be adding error injection API that includes the A53 cores using the TI mechanisms to https://software-dl.ti.com/mcu-plus-sdk/esd/AM64X/latest/exports/docs/api_guide_am64x/SDL_PAGE.html .

The principles for this are the same as in https://software-dl.ti.com/jacinto7/esd/processor-sdk-rtos-jacinto7/latest/exports/docs/sdl/sdl_docs/userguide/j721e/modules/ecc.html but for AM64x this will be in the MCU+ SDK,

Pekka

0 Pekka Varis over 1 year ago in reply to Pekka Varis

TI__Mastermind 24850 points

Looks like AM64x SDL with ECC examples is now live at https://software-dl.ti.com/mcu-plus-sdk/esd/AM64X/latest/exports/docs/api_guide_am64x/EXAMPLES_SDL_ECC.html .

Pekka

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AM6442: How to enable the L1 Cache and L2 Cache ECC Protection on Arm Cortex-A53?