AM3354: Power-Up Sequence Review

Hello Jack,

Thank you for the query.

The sequencing depends on the board configuration.

Please refer below section of the datasheet for possible configurations.

6 Power and Clocking 6.1 Power Supplies 6.1.1 Power Supply Slew Rate Requirement

Figure 6-2. Preferred Power-Supply Sequencing With Dual-Voltage I/Os Configured as 3.3 V

Figure 6-3. Alternate Power-Supply Sequencing With Dual-Voltage I/Os Configured as 3.3 V

Figure 6-4. Power-Supply Sequencing With Dual-Voltage I/Os Configured as 1.8 V

Figure 6-5. Power-Supply Sequencing With Internal RTC LDO Disabled

Figure 6-6. Power-Supply Sequencing With RTC Feature Disabled

Please be sure to check the below power down sequencing. 

6.1.2 Power-Down Sequencing

Please ensure the clock is stable before the reset is released.

We have a TI design that could be referenced. 

https://www.ti.com/tool/TIDA-01568

Regards,

Sreenivasa

The datasheet only has the power-up sequence.

I can't find any mention of timing for each power.

The 10ms timing is based on TIDA-01568.

How much can I reduce the timing interval for each power source?

How many milliseconds should the timing interval for each power source be at least?

It will be designing with the RTC feature disabled.

Hello Jack,

Thank you for the inputs.

I do not see the power sequence timed.

The time interval between supplies must ensure the power supply ramps completely and is stable before the next supply is applied.

A couple of mS should be fine. The ramp time is power supply architecture dependent.

Regards,

Sreenivasa

The time for each power source to reach a stable state is shown below.
 - 1.8V Turn on time: 100us (LDO)
 - 1.5V Turn on time: 3.5ms (DC-DC)
 - 3.3V Turn on time: 200us (LDO)
 - 1.1V Turn on time: 3.5ms (DC-DC)

Q1. Is it okay to design with a minimum time interval of 3.5ms?

Q2. According to the datasheet, the clock signal stabilizes 1.5ms after VDD_CORE voltage is applied.
      And then the PORZ signal can be applied anytime after that?

Hello Jack, 

Thank you for the inputs.

Kyungha Kim said:

The time for each power source to reach a stable state is shown below.
 - 1.8V Turn on time: 100us (LDO)
 - 1.5V Turn on time: 3.5ms (DC-DC)
 - 3.3V Turn on time: 200us (LDO)
 - 1.1V Turn on time: 3.5ms (DC-DC)

Q1. Is it okay to design with a minimum time interval of 3.5ms?

Could you please elaborate what you mean by turn on time and time interval.

Kyungha Kim said:

According to the datasheet, the clock signal stabilizes 1.5ms after VDD_CORE voltage is applied.
      And then the PORZ signal can be applied anytime after that?

This is the typical time and depends on the crystal start up + load cap or the oscillator being used. 

I would suggest designing for X 2 or more of the clock stabilization time.

Regards,

Sreenivasa

Hello Sreenivasa,

Thank you for your response.

Kallikuppa Sreenivasa said:

Could you please elaborate what you mean by turn on time and time interval.

Turn on time means the time it takes for each power source to reach a stable state.

Time interval means the interval between enable signals for each power source.

I want to know the minimum time interval I can design for.

Best Regards,

Kyungha Kim

Hi Sreenivasa

There's no further inquery from the engineer who reported. 

Let's close the thread.  Thanks.

Regards, 

Jack